High Performance Interconnect and Packaging

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High Performance Interconnect and Packaging
Chung-Kuan Cheng
CSE Department UC San Diego ckcheng_at_ucsd.edu
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Research Scope

• Scalable System Power, Delay, Cost, Reliability
• Interconnect-Driven Designs
• Wire Planning Non-Manhattan Interconnect
• Networks Topology, Physical Layout
• Clock Power Shunts Trees (3)
• Interconnect Style Surfliner (2)
• Datapath Shifters, Adders, Mul. Div.
• Packaging Pin Breakaway (1)
• Simulation
• Static Timing Analysis Hierarchy, Incremental
• SPICE Whole System Analysis

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1. Pin Breakaway

• Interfaces of Chip and Package, Package and
  Board.
• Breakaway of Array of Pins
• Patterns of Breakaway
• Obj Cost Breakaway Layers

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1. Pin Breakaway

• Row by Row Escape
• Escape interconnect row by row from outside
  toward inside.

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1. Pin Breakaway (Cont.)

• Parallel Triangular Escape
• This method divides the objects into groups
  and escape each group with a triangular outline.

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1. Pin Breakaway (Cont.)

• Central Triangular Escape
• Escape objects from the center of the outside
  row and expands the indent with a single
  triangular outline.

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1. Pin Breakaway (Cont.)

• Two-Sided Escape
• Escape objects from the inside as well as from
  the outside. The outline shrinks slowly and also
  follow zigzag shape.

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1. Pin Breakaway (Cont.)
Row by Row Parallel Triangles
Central Triangle Two-Sided
The movement of area array contour
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1. Pin Breakaway Design Rules

• Parameters used
• the pad pitch 150?m
• the pad diameter 75?m
• the line width 20?m
• the spacing 20?m

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1. Pin Breakaway Results
40 x 40
Layer Row by row Parallel triangular Central triangular Two sided
1 304 276 100 312
2 272 340 156 328
3 240 292 228 308
4 208 240 300 324
5 176 164 372 328
6 144 124 444
7 112 164
8 80
9 48
10 16
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1. Pin Breakaway Results
20 x 20
Layer Row by row Parallel triangular Central triangular Two sided
1 144 132 92 140
2 112 144 116 160
3 80 96 140 100
4 48 28 52
5 16
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2. Interconnect Style Surfliner

• Global Interconnect trend
• Scalability

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2. Surfliner - Features

• Speed of light
• lt 1/5 Delay of Traditional Wires
• Low Power Consumption
• lt 1/5 Power Consumption
• Robust against process variations
• Short Latency
• Insensitive to Feature Size
• Differential Signaling
• Shield for low swing signals

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2. SurflinerTransmission Line Model
Differential Lossy Transmission Line
Surfliner

• Add shunt conductance G RC/L
• Flat response from DC to Giga Hz
• Telegraph Cable O. Heaviside in 1887.

Shunt conductance G 0 for wires of IC
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2. Surfliner Distortionless Line

• Telegraphers equation

• Propagation Constant

• Wave Propagation

• Alpha and Beta corresponds to speed and phase
  velocity.

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2. Surfliner Distortionless Lines

• Set GRC/L
• Attenuation and Beta

• Characteristic impedance (pure resistive)

• Phase Velocity (Speed of light in the media)

• Attenuation

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2. Surfliner Distortionless Lines
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2. Surfliner Performance

• Speed of Light 5ps/mm or 50ps/cm
• Power 10mW at GHz
• Conductance variation 10, f10MHz10GHz
• Attenuation and velocity variation lt 1

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2. Surfliner Implementation

• Add shunt conductance
• Resistors realized by serpentine unsilicided
  poly, diffusion resistors, or high resistive metal

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2. Surfliner Simulation Results

• Characteristic Impedance (at 10GHz) 39.915 Ohm
• Inductance 0.22nH/mm Capacitance 141fF/mm
• Attenuation 253mv magnitude at receivers end
  (assuming 1V at senders end)
• Using Microstrip (free space above the wires)
  impedance can be improved to 52.8Ohm

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2. Surfliner Settings

• Agilent ADS Momentum extract 4-port S-parameters
• HSpice Transient analysis
• Assume 1023 bit pseudo random bit sequence (PRBS)
• 15GHz clock
• 10 of clock period transition slope for each
  rising and falling edge

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2. Surfliner Simulation Results
120 Stages
4 Stages
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2. Surfliner Simulation

• Jitter and silicon area usage

Stages 4 10 20 40 80 120 160
Jitter (ps) 27 9.5 5.4 4.2 3.9 2.1 2.08
Area (um2) 0.52 3.25 13 52 208 468 832
Power w/ different width and separation
(w, s) (um) (3,3) (4,4) (5,4) (10,5)
Power (mW) 4.98 3.62 3.02 2.13
Attenuation 0.307 0.415 0.496 0.60
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2. Applications of Surfliner

• 1.Clock distributions
• 2. Data communications Buses Between CPUs,
  DSPs, Memory Banks

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2. Application of Surfliner

• 3. High Performance Low Power Wafer Packaging

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2. Surfliner Current Status

• What we have done
• Derived a conservative design
• Performed simulation
• We are looking forward to
• Design and fabricate the test chip
• Explore architectures to exploit the advantages
  of Surfliner

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3. Clock Distribution Shunts Trees

• 3.1 RC Shunts
• 3.2 Inductive Effects
• Contribution
• Analytical skew expression
• Formulation of Multilevel Optimization
• Empirical Observation

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3. Clock Linear Variations Model

• Process variation model
• Transistor length
• Wire width
• Linear variation model
• Power variation model
• Supply voltage varies randomly (10)

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3.1 Clock RC Model

• Input an n level meshes and h-trees
• Constraint routing area, parameter variations
• Objective skew

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Simplified Circuit Model
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Transient Response when tltT
VS1u(t) Vs20 Let
Then V1 A B V2 A - B
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Skew Expression

• Assumptions
• TltltRsC
• Rs /R ltltRsC/T
• Using first order
• Taylors expansion

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Spice Validation of Skew Function
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Skew on mesh

• Conjectured skew expression
• Using regression to get k

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K values for n by n meshes
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Optimization

• Skew function
• Multi level skew function

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Experimental Settings

• Die size 1cm by 1cm
• 100nm copper technology
• Ground Shielded Differential Signal Wires for
  Global Clock Distribution
• Routing area is normalized to the area of a 16 by
  16 mesh with minimal wire width

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Experimental Results

• Optimized wire width

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Optimal Routing Resources Allocation
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Skew reduction V.S. Mesh Area
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ExperimentsOptimized Skew
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Robustness Against Supply Voltage Variations
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3.2 Clock RLC Model

• Motivation RLC shunt effect diminishes in
  multiple-GHz range
• Model of Transmission line
• Formulation of Multilevel Optimization
• Empirical Observation

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3.2 Motivation Inductance Diminishes Shunt
Effects

• 0.5um wide 1.2 cm long copper wire
• Input skew 20ps

f(GHz) 0.5 1 1.5 2 3 3.5 4 5
skew(ps) 3.9 4.2 5.8 7.5 9.9 13 17 26
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3.2 Motivation Synchronization at wavelength
distance
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3.2 Motivation Multilevel Transmission Line
Spiral Network
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3.2 Model of Transmission Line Shunt with Two
Sources

• Transmission Line with exact multiple wave
  length long
• Large driving resistance to increase reflection

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Spice Validation of Skew Equation
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3.2 Model of Transmission Line Multiple Sources
Case

• Random model
• Infinity long wire
• Input phases uniformly distribution on 0, F

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Configuration of Wires

• Coplanar copper transmission line
• height 240nm, separation 2um, distance to
  ground 3.5um, width(w) 0.5 40um

• Use Fasthenry to extract R,L
• Linear R/Lw Relation
• R/L a/wb

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3.2 Formulation of Multilevel Distribution
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Experimental Results

• Set chip size to 2cm x 2cm
• Clock frequency 10.336GHz
• Synthesize H-tree using P-tree algorithm
• Set the initial skew at each level using SPICE
  simulation results under our variation model
• Use FastHenry and FastCap to extract R,L,C value
• Use W-elements in HSpice to simulate the
  transmissionlin

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Optimized Wire Width
Total Area W1 (um) W2 (um) W3 (um) Skew M (ps) Skew S (ps) Impr.()
0 0 0 0 23.15 23.15 0
0.5 1.7 0 0 17.796 20.50 13
1 1.9308 1.0501 0 12.838 14.764 13
3 2.5751 1.3104 1.3294 8.6087 8.7309 15
5 2.9043 3.7559 2.3295 6.2015 6.3169 16
10 3.1919 4.5029 6.8651 4.2755 5.2131 18
15 3.6722 6.1303 10.891 2.4917 3.5182 29
20 4.0704 7.5001 15.072 1.7070 2.6501 37
25 4.4040 8.6979 19.359 1.2804 2.1243 40
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Simulated Output Voltages
Transient response of 16 nodes on transmission
line Signals synchronized in 10 clock cycles
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Simulated Output voltages
Steady state response skew reduced from 8.4ps to
1.2ps
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Power Consumption
Area 3 4 5 7 10 15 20 25
PM(mw) 0.4 0.5 0.7 0.9 1.0 1.4 1.5 1.6
PS(mw) 0.83 1.5 2.1 2.64 3.04 4.7 7.2 8.3
reduce() 48 67 67 66 67 70 79 81
PM power consumption of multilevel mesh PS
power consumption of single level mesh
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Skew with supply fluctuation
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3.2 Future Directions

• Exploring innovative topologies of transmission
  line shunts
• Design clock repeaters and generators
• Actual layout and fabrication of test chip

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Conclusion

• 1 Post Doc., 10 Ph.D. students work on
  interconnect, packaging, and simulation
• Plan to release packages on interconnect planning
  (topology and design style)
• Need help on fabrication and measurement