Basic SYNOPSYS User Guide

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Basic SYNOPSYS User Guide
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Outline
? Setup system environment ? Default Synthesis?
Setting Design SPEC. ? Setting Operating
Environment? Setting Design Constraint -
Combinational circuits -- Timing
constraints - Sequential Circuits --
Specify the clock -- Setting input
delay -- Setting output delay ?
Simulation of Synthesized Circuit
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Setup a New Synopsys User

• Add the contents of /usr/synopsys/cicSynop/synopsy
  s.cshrc to your .cshrc
• hsiehgt cat /usr/synopsys/cicSynop/synopsys.cs
  hrc gtgt .cshrc
• hsiehgt source .cshrc
• hsiehgt design_analyzer
• Use online documentation
• hsiehgt cd
• hsiehgt cp /usr/synopsys/cicSynop/Iview .
• hsiehgt iview

????????
?? Synopsys Design Analyzer
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.synopsys_dc.setup File
? ?.synopsys_dc.setup????? design compiler
????????? cell Library . ?
.synopsys_dc.setup ????????????. ??????? user
???????? . ? ? .synopsys_dc.setup ?????
Library ?????? search_path .
/vlsi-a/Librarys/LIB06_V2/Synopsys/usr/synopsys/li
braries/syn ???????????????? ,
???????VLSI-CAD ?????????? target_library
cb60hp231d.db link_library
cb60hp231d.db symbol_library
cb60hp231d.sdb verilogout_no_tri true

????????? cell library( verilog model) ??synopsys
??????????? .db file(binary file)
?? SYNOPSYS ??? verilog file ???? tri_state
???. (? CADENCE ??? verilog IN ???? tri_state ???)
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Hsieh gt design_analyzer
?? Synopsys Design Analyzer ????
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Default Synthesis
? Read File window ??????? verilog file , ???
OK? (????????? Verilog window , ????)
Read Formats button -- Synopsys formats DB
(binary) .db equation .eq state
table .st -- Verilog .v -- PLA(Berkeley
Espresso) .pla -- EDIF
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Default Synthesis (cont.)
?? ???? Verilog-XL? compile ???? verilog file ,
????? Verilog window ?
Verilog window
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Default Synthesis (cont.)

• ???????
• Syntax error
• verilog ????
• Unsupported statements
• delay, initial, repeat, wait, fork,
  event, deassign, force, release
• Unsupported definitions and declarations
• primitive, time, event, trand, trior,
  tri0, trireg
• Unsupported operators
• and !
• Division operator ( / )
• Modulus operator ( )
• Unsupported gate-level constructs
• nmos, pmos, cmos, rnmos, rpmos, rcmos
• pullup, pulldown
• rtran, tranif0, tranif1, rtranif0, rtranif1

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Default Synthesis (cont.)
? Tools Design Optimization ?? Design
Optimization window ?
??? icon ?,Design Optimization ???????,???? icon
???????(?????????)
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Default Synthesis (cont.)
? ?????????????? ?,?? defaults ????? ?
??????? , ????????? . ?? , ?????????????.
?? SYNOPSYS ? mapping ?????? cells .
???????? icon ?? ?????
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Default Synthesis (cont.)
???
Hierarchical view bottom
???? icon ???? ? icon ?????
???( Hierarchical view )
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Default Synthesis (cont.)
?
????? icon?????????? Symbol view bottom ??????????
Symbol view bottom
????
Symbol view
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Default Synthesis (cont.)

?
????? icon?????????? Schematic view bottom
??????????
Schematic view bottom

Schematic view
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• ??,Synopsys ?????? verilog code ???? (???),
  ??????? Synopsys ?????????? . Synopsys ??? input
  drive is infinite , output capacitance is zero ,
  ?????? Operating conditions, Timing, Area ???
  (??? .synopsys_dc_setup ??????)??????????? ,
  ??????????? Spec. ???????? Constraints , ?
  Synopsys ????????? Design ???? (Optimization) .

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Setting Design SPEC.
Operating Voltage ? Operating temperature
? Process variation ?
My Design
Input Constraints
Output Constraints
Input driving strength ? Input arrival time ?
Output capacitance load?
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Setting Operating Environment
?????????????????????????????,??????,?????????????
????????(???)
??????????????? Shift ??,????????????????????(?
???????)?
???? port ???
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Setting Operating Environment (cont.)
? Attributes Operating Environment
Drive Strength ????? Drive Strength ????(???)
?????? port ?,????? port name ?????????????????
Apply
? ???????????
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Setting Operating Environment (cont.)
??? Operating condition model. (delay model) ?
Cell Library ???????
Name Process Temp volt
Interconnection Model WCCOM 1.33
70.00 4.75
worst_case_tree BCCOM 0.92
0.00 5.25 best_case_tree NCCOM
1.00 25.00 5.00
balance_tree
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Setting Operating Environment (cont.)
??? ????????? ????????
? Cell Library ???????
?? 1000 gates ???
1000 gates ???
2000 gates ???
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Setting Operating Environment (cont.)
? Attributes Operating Environment
Load ????? loading ????(???)
????????? Apply
? ? output loading ??, Synopsys ??? cell
library????????? buffer ( cell library ?????? )
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Setting Design Constraint

• Optimization constraints
• Maximum delay , Minimum delay
• For combinational circuits
• Select the start and end points of the concerned
  paths
• For sequential circuits
• Specify the clock
• Setting input delay
• Setting output delay
• Maximum area

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Combinational circuits
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Setting Constraints (cont.)
? Attributes Optimization Constraints
Design Constraints ?????? Design constraints
window
? Max Area ?? Area ?? (?? gates). ???? license
, ????? power ?? constraint .
? ?????, default ?????
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Combinational circuits
??????????, ? Analysis Highlight
Critical Path , Synopsys ????? Critical Path ??
(??)
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Combinational circuits (cont.)
?? Analysis Report ??? Report ?? (??),
????????? Apply
??? port name
??? Critical path output port (??? port ????,???)
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Combinational circuits (cont.)
Point timing
- Number of cells - Combinational area - Total
area
Operating environment
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Combinational circuits (cont.)
?? constraints ?, ????????? port, ???????? ports
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Combinational circuits (cont.)
? Attributes Optimization Constraints
Timing Constraints ?????? timing constraints
window
Input port name Output port name
? Maximum Delay ???? Input port ? Output port ?
timing constraints
? ????? input ? output ??
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Combinational circuits (cont.)
?????
?????
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Combinational circuits (cont.)
Timing ?? Spec. ?? Synopsys ????? user. Synopsys
???????????.
????? Spec. ????????????? codeing style .
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Combinational circuits (cont.)
output loading ??? 5 pF?, ???????
? cell library ??????
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Combinational circuits (cont.)
?????
Output ??? buffer
?????
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Sequential Circuits
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Specify Clock
? Period ??????(?? ns)
??????? port
Dont Touch Network Do not re-buffer the

clock network Fix hold Fix
your hold time requirement in compile,
create hold constraint for the clock
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Specify Clock (cont.)
? Period ???????? Apply , (?? ns)???? clock
period
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Specify Clock (cont.)
???? duty cycle , ??? clock edge (?????? , Edge
??????????
??? Edge ?????????? enter ????? duty cycle , ???
Apply ??
? ???????? edge ????????????? duty cycle , ???
Apply ??
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Specify Clock (cont.)
?? Propagated bottom ??? skew time (ns) ?? Apply
?? Skew bottom???? clock skew window
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MAX. Delay MIN. DELAY
Input Block
Output Block
My Design
a
e
b
c
d
CLK
t b
????????????,???????????,?? My design?????????????
??,?????, a ???? input delay time???? input block
??????? data ready time,b ????Data ? My design ??
delay time tb ?? Data ? setup time tsu?
e_min
a_min
t su
e_max
a_max
data
data
CLK
a Input Delay
e output Delay
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Setting Input Delay
?????? Attributes Operating Environment
Input Delay ???????????(???)
??????? (??ns) ??Apply
??????? rise,fall delay ,??? icon ???( ???????)
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Setting Output Delay
?????? Attributes Operating Environment
Output Delay ???????????(???)
??????? (??ns) ??Apply
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Setting Constraints -- sequential circuit
?? constraints ?, ????????? port, ???????? ports
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Setting Constraints (cont.) -- sequential circuit
? Attributes Optimization Constraints
Timing Constraints ?????? timing constraints
window
Input port name Output port name
? Maximum Delay ???? Input port ? Output port ?
timing constraints ? ????? input ? output ??
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Setting Constraints (cont.) -- sequential circuit
? ????? Synopsys ? combinational circuit ?
sequential circuit ?? Critical Path????? .
????????????? Critical Path.
??????????, ? Analysis Highlight
Critical Path , Synopsys ????? Critical Path ??
(??)
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Setting Constraints (cont.) -- sequential circuit
Output name
?????? gate output point (??????), ? Analysis
Show Timing??????? timing . ?? Report ??.
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Setting Constraints (cont.) -- sequential circuit
????(????? gate) ? Analysis Highlight
Max Path Max Path ??????? timing path .(??????)
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Setting Constraints (cont.) -- sequential circuit
Max. delay time
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Setting Constraints (cont.) -- sequential circuit
?????? input port ? gate output point (?????).
????????.
input port name
gate output point name
??????? (??ns) ??Apply
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Setting Constraints (cont.) -- sequential circuit
???????? input port ????????? gate ?output
point(??)
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Setting Constraints (cont.) -- sequential circuit
?????
?????
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Setting Constraints (cont.) -- sequential circuit
Max. delay time
Max. delay time
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Setting Constraints (cont.) -- sequential circuit
? ?? latch or flip flop ???? constraints ?
delay time ?? spec.
????, ?? delay time ?? spec.????????.??? 5254
?????.
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Setting Constraints (cont.) -- sequential circuit
? ???????????
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Setting Constraints (cont.) -- sequential circuit
????????? ,??? icon . ???? from point
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Setting Constraints (cont.) -- sequential circuit
??????output point
??????? (??ns) ??Apply
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Setting Constraints (cont.) -- sequential circuit
?????
?????
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Setting Constraints (cont.) -- sequential circuit
??? Delay time
??? Delay time
????? gate
?? timing SPEC.
?? 43 44 ??????? Max. Path
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• Differences of coding
• structure
• key word --- //synopsys

??????? SYNOPSYS on line document --- HDL
Compiler for Verilog Reference
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Structure
Coding ?????????????, synopsys ??? user??? Coding
??????, ????????. ???????? HDL Compiler for
Verilog Reference --- Chapter 8 (SYNOPSYS on line
document).???????.
module coding_1(a, b, c, d, out) input 30 a,
b, c, d reg 30 outtmp output 30
out always _at_(a or b or c or d) begin outtmp a
b c d end assign out outtmp endmodule
module coding_2(a, b, c, d, out) input 30 a,
b, c, d reg 30 outtmp output 30
out always _at_(a or b or c or d) begin outtmp
((a b) (c d)) end assign out
outtmp endmodule
difference
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Coding_1 out a b c d
Coding_2 out ((a b ) (c d))
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Coding_1
Coding_2
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key word --- //synopsys
module SP1 ( reset,SP2IB1,IB12SP,SPen,
SP2IB1en ) input SPen, SP2IB1en
,reset input 20 IB12SP output 20
SP2IB1 reg 20 sp always _at_(SPen or IB12SP
or reset) begin if (reset) sp 07
else if (SPen) sp IB12SP end assign
SP2IB1 (SP2IB1en ? sp 'bz) endmodule
module SP2 ( reset,SP2IB1,IB12SP,SPen,
SP2IB1en ) input SPen, SP2IB1en
,reset input 20 IB12SP output 20
SP2IB1 reg 20 sp //synopsys async_set_reset
"reset" always _at_(SPen or IB12SP or reset) begin
if (reset) sp 07 else if (SPen)
sp IB12SP end assign SP2IB1 (SP2IB1en ?
sp 'bz) endmodule
Coding_1
Coding_2
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? ???? //synopsys async_set_reset ?,
SYNOPSYS?????? set or reset ? latch. ??
SYNOPSYS ?? reset ? enable signal ? gated control
?? latch ? enable input, ????????????????.
Coding_1
Coding_2
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key word --- //synopsys
module CIN1(C2CIN ,IB172CIN ,CINout ,CINsel
,CINen ,CINclr) input C2CIN, IB172CIN, CINen,
CINclr input 10 CINsel output CINout reg
muxans,cin always _at_(CINsel or C2CIN or
IB172CIN) begin case(CINsel) //synopsys
full_case parallel_case 2'b00 muxans
C2CIN 2'b01 muxans C2CIN 2'b11 muxans
IB172CIN //default muxans
1'bx endcase end //synopsys
async_set_reset "CINclr" always _at_(muxans or
CINen or CINclr) begin if (CINclr) cin
0 else if (CINen) cin muxans
end assign CINout cin endmodule
module CIN2(C2CIN ,IB172CIN ,CINout ,CINsel
,CINen ,CINclr) input C2CIN, IB172CIN, CINen,
CINclr input 10 CINsel output CINout reg
muxans,cin always _at_(CINsel or C2CIN or
IB172CIN) begin case(CINsel) 2'b00
muxans C2CIN 2'b01 muxans C2CIN 2'b11
muxans IB172CIN
//default muxans 1'bx
endcase end //synopsys async_set_reset "CINclr"
always _at_(muxans or CINen or CINclr) begin
if (CINclr) cin 0 else if (CINen)
cin muxans end assign CINout
cin endmodule
??? full_case ???, ?? case ??.
Coding_1
Coding_2
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Coding_1
Coding_2
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Additional Setting
??????? SYNOPSYS on line document --- Design
Compiler Family Reference Manual
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Check Design
???? Report
???????
???? errors ? warnings ???????, ??????????
?? Check Design ????????? .
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Command Window
command window ??? user ???????????????
success
fail
?????
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?????
????
????
? Variables window ??? user ??????.
?????verilogout_no_tri ???? false ??? true (????
.synopsys_dc_setup ??)
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Simulate the Synthesized Circuit
???????
(1) Save the synthesized circuit as verilog
format ( .v)
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Simulate the Synthesized Circuit(cont.)
(2) Simulation ??? Verilog XL command line
simulation method ex) ?????? pattern ? test.v
hsiehgt verilog incr.v test.v -f
/simopt.f ?? , incr.v ????
Synopsys ??? verilog file
simopt.f ??? library ????? (User ??
, ???) ??? Verilog In Verilog
In?? Cadence ??? , ? netlist ?? schematic ???
. ?? Verilog In ??? netlist , ???? Synopsys ?
??? verilog file ?????? behavior level ??? ,
??? ???? Verilog In ??? schematic ???? ??? ,
??? ????????,??? Synopsys ??? verilog file ,
??? ??? Verilog In???? ????? ?
.synopsys_dc.setup ???,?? verilogout_no_tri
false ????verilogout_no_tritrue ?????

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Variables of Verilog and Simopt.f file
Variables of Verilog -s
interactive mode -f lt filename gt read
host command arguments from file venv
invoke the verilog control window and
LSE -h help
simopt.f ?????? ism -v
/vlsi-a/Librarys/LIB06_V2/Verilog/cb60hp231d.ismvm
d -v /vlsi-a/Librarys/LIB06_V2/Verilog/cb60hd23
1d.ismvmd -v /vlsi-a/Librarys/LIB06_V2/Verilog/
cb60io420d.ismvmd -v /vlsia/Librarys/LIB06_V2/V
erilog/cb60hp231d/cells/support/udps.vmd -v
/vlsi-a/Librarys/LIB06_V2/Verilog/cb60hd231d/cells
/support/udps.vmd
nonlinear model
linear model
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• Reference
• SYNOPSYS on line document
• --- Design Compiler Family Reference Manual
• --- HDL Compiler for Verilog Reference
• CIC ????
• --- Login Synthesis Training Manual

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