Algorithmic State Machines (ASM) part 1

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Algorithmic State Machines(ASM)part 1
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Algorithmic State Machine (ASM)?

• Our design methodologies do not scale well to
  real-world problems. Take this

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Algorithmic State Machine (ASM)?

• Procedure for implementing a problem with a given
  piece of equipment.
• Define digital algorithmic solutions for
  hardware.
• Resembles a conventional flow chart but
  interpreted differently
• ASM described the sequence as well as the timing
  of events.
• Adapted to specify the control sequence and data
  processing operations.

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Control and datapath

• A digital system can be split into two
  components
• Datapath unit Manipulates data according to the
  system requirements.
• Control unit Generates the signals for
  sequencing the operations in the data processor.
• Figure 8.2 Control and datapath interaction

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State box

• Figure 8.3 ASM chart state box

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Decision box

• Figure 8.4 ASM chart decision box

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Conditional box
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ASM block

• One entrance path
• Any number of exit paths
• Describes the state of the systems during one
  clock-pulse interval.
• The operations within the state and the
  conditional boxes are executed with a common
  clock pulse while the system is in state S_0.

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ASM chart State diagram
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Timing

• All the following operations occur
  simultaneously
• A ? A1
• If E 1 then R ? 0
• Depending on E and F, the state is changed to
  S_1, S_2 or S_3.

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Design problem

• Design a digital system with two flip-flops, E
  and F, and one 4-bit binary counter, A. The
  individual flip-flops of A are denoted by
  A4,A3,A2, and A1, with A4 holding the MSB. A
  start signal S initiates system operation by
  clearing the counter A and the flip-flop F. The
  counter is then incremented by 1 starting from
  the next clock pulse and continues to increment
  until the operations stop. Counter bits A3 and A4
  determine the sequence of operations
• If A3 0, E is cleared to 0 and the count
  continues.
• If A3 1, E is set to 1 then if A4 0, the
  count continues, but if A4 1, F is set to 1
  on the next clock pulse and the system stops
  counting.

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ASM Chart

• Design a digital system with two flip-flops, E
  and F, and one 4-bit binary counter, A. The
  individual flip-flops of A are denoted by
  A4,A3,A2, and A1, with A4 holding the MSB. A
  start signal S initiates system operation by
  clearing the counter A and the flip-flop F. The
  counter is then incremented by 1 starting from
  the next clock pulse and continues to increment
  until the operations stop. Counter bits A3 and A4
  determine the sequence of operations
• If A3 0, E is cleared to 0 and the count
  continues.
• If A3 1, E is set to 1 then if A4 0, the
  count continues, but if A4 1, F is set to 1
  on the next clock pulse and the system stops
  counting.

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The datapath
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State diagram for control
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Algorithmic State Machines(ASM)part 2
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Datapath for binary multiplier

• Sum only two binary numbers accumulating the
  partial sums in Register Q.
• Instead of shifting the multiplicand to the left,
  shift the product to the right

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ASM for binary multiplier

• P the number of bits in the registers

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Control Logic

• Signals to be generated
• T0-T3
• L (The Load signal for Register A, that allows
  the loading of the output of the binary adder.

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Control Circuit implemented with D flip-flops
Dec
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ASM with four control inputs

• Operations are left blank.
• We are interested in the design of the control
  part only.
• Four control inputs w, x, y, z
• Four states T0-T3 needs 2 flip-flops.

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Using MUXes to implement the control logic

• Two D flip-flops encode the state.
• The state is decoded into state signals T0-T3 by
  a decoder.
• The current state multiplexes the next state.
• Challenge how to set the inputs of the MUXes?

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The complete circuit
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Count-of-Ones

• The system consists of two registers R1 and R2
  and a flip-flop E.
• The system counts the number of 1s in the number
  loaded into R1 and set R2 to that number.
• Shift one bit from R1 into E.
• If E 1 then R2
• If Z 1 (that is R1 0) then stop.
• R2 is initialized to all 1s. Why?

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Datapath for Count-of-Ones
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Control logic for Count-of-Ones