High speed InP-based heterojunction bipolar transistors

1
High speed InP-basedheterojunction bipolar
transistors
2001 ISCS Conference, October, Tokyo

• Mark Rodwell
• University of California, Santa Barbara

rodwell_at_ece.ucsb.edu 805-893-3244, 805-893-3262
fax
2
How to Improve the Bandwidth of Bipolar
Transistors ?
Thinner base, thinner collector higher ft ,
but higher Rbb, Ccb what parameters are really
important in HBTs ?how do we improve HBT
performance ?
3
HBT scaling transit times
21 improved device speed keep G's, R's, I's,
V's constant, reduce 21 all C's, t 's
reduce Tb by Ö21 tb improved 21 reduce Tc
by 21 tc improved 21 note that Ccb has
been doubled ..we had wanted it 21 smaller
4
HBT scaling lithographic dimensions
21 improved device speed keep G's, R's, I's,
V's constant, reduce 21 all C's, t 's
Base Resistance Rbb must remain constant Le
must remain constant
Ccb/Area has been doubled ..we had wanted it 21
smaller must make areaLeWe 41 smaller must
make We Wc 41 smaller
reduce collector width 41reduce emitter width
41 keep emitter length constant
5
HBT scaling emitter resistivity, current density
21 improved device speed keep G's, R's, I's,
V's constant, reduce 21 all C's, t 's
Emitter Resistance Rex must remain constantbut
emitter areaLeWe is 41 smaller resistance per
unit area must be 41 smaller
Collector current must remain constantbut
emitter areaLeWe is 41 smaller and collector
areaLcWc is 41 smaller current density must be
41 larger
increase current density 41reduce emitter
resistivity 41
6
Scaling Laws for fast HBTs
for x 2 improvement of all parasitics ft, fmax,
logic speedbase Ö2 1 thinnercollector 21
thinneremitter, collector junctions 41
narrowercurrent density 41 higheremitter Ohmic
41 less resistive
transferred-substrate
undercut-collector
Challenges with ScalingCollector mesa HBT
collector under base Ohmics. Base Ohmics must be
one transfer lengthsets minimum size for
collector Emitter Ohmic hard to improvehow
?Current Density dissipation, reliabilityLoss
of breakdownavalanche Vbr never less than
collector Egap (1.12 V for Si, 1.4 V for InP)
.sufficient for logic, insufficient for power
Narrow-mesa with 1E20 carbon-doped base
7
UCSBONR
Transferred-Substrate HBT Process Flow
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Ultra-high fmax Transferred-Substrate HBTs
Michelle Lee

• Substrate transfer provides access to both sides
  of device epitaxy
• Permits simultaneous scaling of emitter and
  collector widths
• Maximum frequency of oscillation
• Sub-micron scaling of emitter and collector
  widths has resulted in record values of
  extrapolated fmax
• Extrapolation begins where measurements end
• New 140-220 GHz Vector Network Analyzer (VNA)
  extends device measurement range

30
Mason's
3000 Å collector 400 Å base with 52 meV
grading AlInAs / GaInAs / GaInAs HBT
gain, U
25
20
Gains, dB
MSG
H
f
1.1 THz ??
21
max
f
204 GHz
Emitter, 0.4 x 6 mm2
t
Collector, 0.7 x 6 mm2
I
6 mA, V
1.2 V
c
ce
10
100
1000
Frequency, GHz
9
220 GHz On-Wafer Network Analysis
Miguel Urteaga
140-220 GHz network analysis HP8510C network
analyzer Oleson Microwave Lab frequency
Extenders GGB waveguide-coupled probes 75-100
GHz network analysis GGB waveguide-coupled probes
HP W-band test set 1-50 GHz network
analysis GGB coax-connectorized probes HP
0.045-50 GHz test set
10
Accurate Transistor Measurements Are Not Easy

• Submicron HBTs have very low Ccb (lt 5 fF)
• HBT S12 is very small
• Standard 12-term VNA calibrations do not correct
  S12 background error due to
  probe-to-probe coupling
• Solution
• Embed transistors in sufficient length of
  transmission line to reduce coupling
• Place calibration reference planes at transistor
  terminals
• Line-Reflect-Line Calibration
• Standards easily realized on-wafer
• Does not require accurate characterization of
  reflect standards
• Characteristics of Line Standards are well
  controlled in transferred-substrate microstrip
  wiring environment

Transistor in Embedded in LRL Test Structure
Corrupted 75-110 GHz measurements due
to excessive probe-to-probe coupling
11
Can we trust the calibration ?
Miguel Urteaga
140-220 GHz calibration looks OK
75-110 GHz calibration looks Great
S11 of open About 0.1 dB / 3o error
S11 of through About 40 dB
S11 of short
S11 of open
S11 of through
Probe-Probe coupling is better than 45 dB
S21 of through line is off by less than 0.05 dB
dB
12
Submicron transferred-substrate HBTs
0.25 mm emitter-base junction
0.4 mm Schottky collector
13
UCSBONR
Submicron InAlAs/InGaAs HBTs Unbounded (?!?)
Unilateral power gain 45-170 GHz
Miguel Urteaga
emitter
collector
Emitter 0.3 x 18 ?m2, Collector 0.7 x 18.6
?m2Ic 5 mA, Vce 1.1 V
Gains are high at 200 GHz but fmax cant be
determined
14
Negative Unilateral Power Gain ???
Can U be Negative?
YES, if denominator is negative This may
occur for device with a negative output
conductance (G22) or some positive feedback (G12)
What Does Negative U Mean?
Device with negative U will have infinite
Unilateral Power Gain with the addition of a
proper source or load impedance
AFTER Unilateralization

• Network would have negative output resistance
• Can support one-port oscillation
• Can provide infinite two-port power gain

Select GL such that denominator is zero
Simple Hybrid- ? HBT model will NOT show negative
U
15
Ccb Cancellation by Collector Space-Charge
Moll Camnitz, Betser and Ritter
Collector space charge screens field,
Increasing voltage decreases velocity,
modulates collector space-charge offsets
modulation of base charge Ccb is reduced
measured 0.64 fF decrease
Ccb total
Ic
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UCSB
175 GHz Single-Stage Amplifier
Miguel Urteaga
Submicron HBT Program
6.3 dB gain at 175 GHz
17
UCSB
295 GHz f?, fmax HBT
Yoram Betser
2000 Å collector 300 Å base with 52 meV
grading AlInAs / GaInAs / GaInAs HBT
Emitter 1 x 8 ?m2, Collector 2 x 8.5 ?m2.
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Fast InP DHBTs
UCSB
pk Sundararajan M Dahlstrom
3 kÅ collector, 400 Å base
1x 8 micron emitter, 2x 10 micron collector
5 V breakdown at 105 A/cm2 gt9 V at 2104 A/cm2
ft 165 GHz fmax 303 GHz
2 kÅ collector, 400 Å base
1x 8 micron emitter, 2x 10 micron collector
4 V breakdown at 105 A/cm2 gt6 V at 2104 A/cm2
ft 216 GHzfmax 210 GHz
19
UCSB
InGaAs/InP DHBT, 3000 Å InP collector
Sangmin Lee
fmax 425 GHz, ft 139 GHz
BVCEO 8 V at JE 5104 A/cm2
0.5 ?m x 8 ?m emitter (mask) 0.4 ?m x 7.5 ?m
emitter (junction) 1.2 ?m x 8.75 ?m
collectorIc4.5 mA, Vce1.9 V
20
Is low DHBT ft due to base-collector grade ?
100 Å grade
480 Å grade
collector velocity and grade InP has higher
Gamma-L separation than InGaAs? Vsat should be
higher in InP ? ft should be higher, not
lowerslow transport in InAlAs ? ? thin grade !
21
Narrow-Mesa HBTs high fmax if high base doping
0.5 mm emitter, 0.25 mm base contacts
22
InP/InGaAs/InP Metamorphic DHBTon GaAs substrate
 
 
UCSB
Growth 400 Å base, 2000 Å collector
GaAs substrate InP metamorphic buffer
layer (high thermal conductivity) Processing
conventional mesa HBT narrow 2 um base
mesa Results 165 GHz ft, 92 GHz fmax, 6
Volt BVCEO, b27
triple-mesa device (not transferred-substrate)
165 GHz ft 92 GHz fmax
 
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UCSB
High Speed Amplifiers
Dino MensaPK Sundararajan
18 dB, DC--50 GHz
S21
gt397 GHz gain x bandwidth from 2 HBTs
S11
S22
8.2 dB, DC-80 GHz
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HBT distributed amplifier
UCSB
AFOSR
11 dB, DC-87 GHz
PK Sundararajan
TWA with internal ft-doubler cells
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UCSB
18 GHz S-D ADC
S Jaganathan
Design comparator is 75 GHz flip flop DC bias
provided through 1 K? resistors Integration
obtained with 3 pF capacitors RTZ gated DAC
Integrated Circuit150 HBTs, 1.2 x 1.5 mm, 1.5 W
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75 GHz HBT master-slave latchconnected as
Static frequency divider
UCSB
Thomas MathewHwe-Jong Kim
technology 400 Å base, 2000 Å collector HBT
0.7 um mask (0.6 um junction) x 12 um emitters
1.5 um mask (1.4 um junction) x 14 um collectors
1.8105 A/cm2 operation, 180 GHz ft, 260 GHz
fmax simulations 95 GHz clock rate in SPICE test
data to datetested, works over full 26-40 and
50-75 GHz bands
3.92 V, 224 mA, 0.88 W
3.5 dBm input power
modulation is synthesizer 6 GHz subharmonic
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MHBT slide
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Logic Speed III-V vs. Silicon
0.1 um
0.15 um
Benchmark master-slave flip-flop configured as
21 static frequency dividerSource M Sokolich,
HRL, Rodwell, UCSB
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State-of-art in HBTs, 2000 cutoff frequencies
0.1 um emitters
1 um emitters(0.4 um)
(UCSB t.s. device)
1 um emitters
InP HBTs today 2x faster, more scalable
Johnson limit, 2x faster at 5x larger dimensions
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State-of-Art in HBTs, 2000 small-scale circuits
Si / SiGe has rough parity in logic with InP
despite lower ft, fmax due to higher current
density, better emitter contacts Si/SiGe has
significantly slower amplifiers
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What do we need for fast logic ?
ECL M-S latch
Neither ft nor fmax predicts digital speed
CcbDVlogic/Ic is very important collector
capacitance reduction is critical increased
III-V current density is critical Rex must be
very low for low DVlogic at high Jc InP Rbb ,
(tbtc) , are already low, must remain so
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What HBT parameters determine logic speed ?
Caveats assumes a specific UCSB InP HBT (0.7 um
emitter, 1.2 um collector 3kÅ thick, 400 Å base,
1.5E5 A/cm2) ignores interconnect capacitance
and delay, which is very significant
33
Why isn't basecollector transit time so
important ?
34
Very strong features of Si-bipolars
Emitter Width0.1 um Emitter Current Density10
mA/um2 Polysilicon Emitter Contactmetal-semicondu
ctor contactarea gtgt emitter junction area low
RexPolysilicon base contactlow sheet
resistance in extrinsic basesmall extrinsic
collector-base junction area
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InP HBT limits to yield non-planar process
Failure modes
Emitter contact
Etch to base
Liftoff base metal
Emitter planarization, interconnects
Yield degrades as emitters are scaled to
submicron dimensions
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Submicron HBT scaling
Scaling HBTs for 2 x increased speed 2 x
thinner layers, 4 x narrower junctions 4 x
higher current density, 4 x improved vertical
contacts Results with submicron III-V HBT
scaling 300 GHz ft , high (unmeasurable)
fmax 6-dB 175 GHz amplifiers, 75 GHz true
digital ICs Challenges with HBT scaling for fast
digital collector width scaling, current
density, emitter resistivity high-yield
submicron emitter collector processes
37
In Case of Questions
38
Scaling Laws, Collector Current Density, Ccb
charging time
Base Push-Out (Kirk Effect)
Collector Depletion Layer Collapse
Collector capacitance charging time is reduced
by thinning the collector while increasing
current