Ultra high speed heterojunction bipolar transistor technology

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Ultra high speed heterojunction bipolar
transistor technology
2001 GOMAC Conference

• Mark Rodwell
• University of California, Santa Barbara

rodwell_at_ece.ucsb.edu 805-893-3244, 805-893-3262
fax
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Scaling and high speed electronics

• Fast electronics 10, 40,160 (?) Gb/s fiber
  opticsGigabit radio on 60 GHz band 180 GHz
  amplifiers, sensitive 2.5 THz diode
  mixerscheap 2 GHz phones, cheap 1 GHz PCs, cheap
  20 GHz TVelectronics gets 101 faster each
  decade
• Are we reaching the limits ?...radically
  different materials ?...resonant tunneling
  ??the electronic bottleneck ?
• Improving high frequency devices by
  Scalingdimensions, current density,
  contactsnear-THz transistors, 10 THz diodes,
  towards 100-GHz logic ? applications in
  ADCs/DACs for RADAR
• Fast electronics can still get much faster

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Bandwidth of bipolar transistors current-gain
cutoff frequency
Thinner base, thinner collector higher ft ,
but.
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Bandwidth of bipolar transistors power-gain
cutoff frequency
Thinner base, thinner collector more base
resistance, more collector capacitance reduced
power gain cutoff frequency fmaxWhat matters
ft or fmax ?How do we scale device to get high
values for both ?
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Scaling Laws for fast HBTs
for x 2 improvement of all parasitics ft, fmax,
logic speedbase Ö2 1 thinnercollector 21
thinneremitter, collector junctions 41
narrowercurrent density 41 higheremitter Ohmic
41 less resistive
transferred-substrate
undercut-collector
Challenges with ScalingCollector mesa HBT
collector under base Ohmics. Base Ohmics must be
one transfer lengthsets minimum size for
collector Emitter Ohmic hard to improvehow
?Current Density dissipation, reliabilityLoss
of breakdownavalanche Vbr never less than
collector Egap (1.12 V for Si, 1.4 V for InP)
.sufficient for logic, insufficient for power
Narrow-mesa with 1E20 carbon-doped base
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What HBT parameters determine analog bandwidth ?
Tuned ICs (MIMICs, RF)fmax sets gain, max
frequency, not ft. low ft/fmax ratio makes
tuning design hard (high Q)
Lumped analog circuitsneed high comparable ft
and fmax. (1.51 fmax/ft ratio often cited as
good)
Distributed Amplifiersin principle,
fmax-limited, ft not relevant.(low ft makes
design hard)
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What HBT parameters determine logic speed ?
MS latch key digital element resynchronizes
data to clock often sets system maximum clock
fmax does not predict digital speed ft does not
predict digital speed CcbDVlogic/Ic is very
important increased III-V current density is
critical CcbRex is very important Rbb(Cjegmtbgmt
c) is important
120 GHz clock predicted
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What is needed for 200 GHz Logic ?
UCSB
Miguel Urteaga
SPICE simulation Interconnects are not
considered.
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Transferred Substrate HBTs
finite-element device simulation

• UCSB transferred substrate process allows
  lateral scaling of collector. Record fmax more
  than tripled.
• Most circuits demand high ft. Laterally scalable
  device allows fmax to be retained when ft is
  improved by vertical scaling.

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Submicron Transferred-Substrate HBT
UCSB
Michelle Lee
3000 Å collector 400 Å base with 52 meV
grading AlInAs / GaInAs / GaInAs HBT
(?)
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UCSB
High Fmax Transistor Measurement
Miguel Urteaga
Submicron HBT Program
( Klt 1 at all measured frequencies)
140-220 GHz Unilateral power gain high but
difficult to measure fmax appears to be
near 1 THz.Future work must address
improved 220 GHz measurements, measurements
at gt 220 GHz.
U
MSG
Unpublished
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UCSB
Record f? HBT
Yoram Betser
2000 Å collector 300 Å base with 52 meV
grading AlInAs / GaInAs / GaInAs HBT
Emitter 1 x 8 ?m2, Collector 2 x 8.5 ?m2.
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UCSB
Record f? HBT
Yoram Betser
290fs
82fs
20fs
39fs
537fs
105fs
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Fast InP DHBTs for higher power
UCSB
6.2 DHBT program
pk Sundararajan M Dahlstrom
3 kÅ collector, 400 Å base
1x 8 micron emitter, 2x 10 micron collector
5 V breakdown at 105 A/cm2 gt9 V at 2104 A/cm2
ft 165 GHz fmax 303 GHz
2 kÅ collector, 400 Å base
1x 8 micron emitter, 2x 10 micron collector
4 V breakdown at 105 A/cm2 gt6 V at 2104 A/cm2
ft 216 GHzfmax 210 GHz
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UCSB
200 GHz Single-Stage Amplifier
Miguel Urteaga
Submicron HBT Program

• Single-stage Reactively-tuned amplifier at 180
  GHz with 6 dB gain
• Gain-per-stage 21 higher than HEMT amplifiers
  at same frequency
• Simple design to provide directions for future
  work
• Future Work Multi-stage amplifiers with
  improved devices

Measured Gain
Measured Return Loss
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InP-HBT W-band Amplifiers
UCSB
ARO
James Guthrie
common-base amplifier 9.7dBm at 82.5 GHz
balanced amplifier 10.7dBm at 78GHz
(transferred-substrate HBT)InGaAs-collector
Vbr1.5 V low powerInP-collector
Vbr5 V higher powers expected
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UCSB
High Speed Amplifiers
Dino MensaPK Sundararajan
18 dB, DC--50 GHz
S21
gt397 GHz gain x bandwidth from 2 HBTs
S11
S22
8.2 dB, DC-80 GHz
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HBT distributed amplifier
UCSB
AFOSR
11 dB, DC-87 GHz
PK Sundararajan
TWA with internal ft-doubler cells
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75 GHz HBT master-slave latchconnected as
Static frequency divider
UCSB
Thomas MathewHwe-Jong Kim
200 GHz Logic Program
re-fabricated 1999 (Q. Lee) UCSB design In
1999 operated to 66 GHz limit of available
sources technology 400 Å base, 2000 Å
collector HBT 0.7 um mask (0.6 um junction) x
12 um emitters 1.5 um mask (1.4 um junction) x
14 um collectors 1.8105 A/cm2 operation, 180
GHz ft, 260 GHz fmax simulations 95 GHz clock
rate in SPICE test data to datetested, works
over full 26-40 and 50-75 GHz bandsnow testing
in 75-110 GHz band (limited signal power)
3.92 V, 224 mA, 0.88 W
3.5 dBm input power
modulation is synthesizer 6 GHz subharmonic
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19 GHz adder-accumulator
UCSB
Thomas Mathew
Objectives 40-60 GHz clock rate adder for 20
GHz DDS Approachbuilding blocks for a pipelined
adder Simulations 40-60 GHz clock rate in
SPICE SignificanceDesign to meet 20GHz DDS
requirements StatusComponent blocks built,
working at 19 GHz
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UCSB
20 GHz S-D ADC
S Jaganathan
ONR ADC Program
Design comparator is 75 GHz flip flop DC bias
provided through 1 K? resistors Integration
obtained with 3 pF capacitors RTZ gated DAC
Integrated Circuit150 HBTs, 1.2 x 1.5 mm, 1.5 W
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Submicron device scaling towards THz bandwidths
Scaling drift-diffusion electron devices for 2 x
increased speed 2 x thinner layers, 4 x
narrower junctions 4 x higher current density, 4
x improved vertical contacts Results with
submicron III-V HBT scaling 300 GHz ft , high
(1100 GHz ?) fmax Challenges with scaling power
density, improved vertical contacts,
breakdown Opportunities aggressive parasitic
reduction of III-V's (as in Silicon) III-V HBT
scaling to below 0.1 um Prognosis much faster
transistors, amplifiers, and logic are still
feasible
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In Case of Questions
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Submicron Transferred-Substrate HBT
UCSB
Michelle Lee
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Why Masons Gain, U, is used to find fmax
MAG/MSG canbe below U
MAG/MSG canbe above U
below -20 dB/dec line
...above -20 dB/dec line
(CE, small Ccbx )
( CE, large Ccbx )
U is not changed by pad parasitics U has -20 dB /
decade slope to fmax MSG slope is -10 dB /
decade MAG has no fixed slope -for
hybrid-p model comment U is not given by
U is same forCE , CB, CC
Plots generated using HP / EESOF simulator and
standard hybrid-p model
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Measuring High fmax Transistors I
DC-50 GHz 75-110 GHz Network Analysis
waveguide-coupled micro-coax probes Parasitic
probe-probe coupling S12 error background
not corrected by calibration gain
measurements corrupted, worse for W-band
corrupted W-band measurement
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Measuring High fmax Transistors II
Offset reference planes, on-wafer LRL calibration
standards separate probes to reduce
coupling reference planes at transistor
terminals
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Line-reflect-line on-wafer cal. standards
Lo1275 mmLo
20-60 GHz LINE 75-110 GHz LINE THROUGH
LINE SHORT OPEN (reflect) DUT
Lo560 mmLo
LoLo
20-60 GHz Calibration standards
75-110 GHz Calibration standards
Lo
Lo
Calibration verification
Lo
Lo
V 2.04 x 108 m/s (er 2.7)
Lo
Lo
Device under test
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185 GHz Single-Stage Amplifier High fmax
demonstration
6.2 Submicron HBT Programalso supported by AFOSR

• Single-stage reactively-tuned amplifier at 185
  GHz with 3.0 dB gain
• Gain-per-stage is comparable to results from
  HEMT technologies
• Simple design to provide directions for future
  work
• Future Work Multi-stage amplifiers with
  improved devices

Measured Gain
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Ultra-High fmax Transferred-Substrate HBTs
6.2 Submicron HBT Program

• Transferred-substrate process results in
  dramatic reduction in collector base capacitance
  (Ccb)
• Sub-micron scaling of emitter and collector
  widths has resulted in record values for
  extrapolated fmax (1 THz)
• Improved E-beam lithography at UCSB will allow
  more aggressive device scaling
• Reduce base resistance with carbon base doping
  and improved base Ohmics
• Goal Build the Worlds Fastest Electron
  Device

Sub-micron HBT measured from 0-50 GHz and 140-220
GHz High speed device measurements require
careful attention to measurement and calibration
methodology