THE ARITHMETIC-LOGIC UNIT

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THE ARITHMETIC-LOGIC UNIT
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BINARY HALF-ADDER
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BINARY HALF-ADDER condt
Half adder
Input Input Output Output
X Y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Karnaugh Map and formulae for S

0 1
1 0
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FULL ADDER
Inputs Inputs Inputs Outputs Outputs
X Y Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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Karnaugh Map and formulae for S

0 1 0 1
1 0 1 0
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Karnaugh Map and formulae for carry out

0 0 1 0
0 1 1 1
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FULL ADDER condt
Half adder
1
1
Half adder
S2
2
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FULL ADDER condt
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FULL ADDER (IBM version)
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FULL ADDER (IBM version) condt
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PARALLEL ADDER
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Applying the parallel adder for addition of
natural numbers

• Examples
• a) b)

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Applying the parallel adder for addition of
integers in 2s complement code Examples a)
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Example b)
Skip!
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Example c)

Skip!
Contradiction because
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Applying the parallel adder for addition of
integers in 1s complement code Example a)
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Example b)
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Parallel addition and subtraction
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Basic logic operations
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Shift operations
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Generalized parallel arithmetic element
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Problems encountered during multiplication
Multiplicand
Multiplier
Partial products
Product
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Operations to be performed by ALU during
multiplication

• To sense whether a given bit is 1 or 0
• To shift left partial products
• To add the partial products.

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Basic steps during multiplication

• The accumulator is reset to 0, the multiplicand
  is load to the register Y and the multiplier is
  load to the register B.

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Basic steps during multiplication condt

• The following basic step is repeated n times
  where n is the number of bits in magnitude part
  of the numbers being multiplied
• 10 If the rightmost bit in the B register is a 0,
  the combined accumulator and B register are
  shifted right one place.
• 20 If the rightmost bit in the B register is a 1,
  the number in Y register is added to the contents
  of the accumulator, and then the combined
  accumulator and B register are shifted right one
  place.
• When basic steps are finished, the contents of
  the combined accumulator and the B register
  consist of the product being derived. The sign of
  it is set by a separate circuit.

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Example
Product 00011101012
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Problems encountered during division
a)
Quotient
Dividend
Divisor
Remainder
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Problems encountered during division condt
b)
Quotient
Dividend
Divisor
Remainder
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Problems encountered during division condt
c)
Quotient
Dividend
Divisor
Remainder
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Description of the division procedure

• Before the procedure starts, the B register is
  reset to 0, the dividend is read into the
  accumulator and the divisor into the Y register.
  After the division, the quotient is stored in the
  B register, and the remainder in the accumulator.
  Both divisor and dividend are to be positive.

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Description of the division procedure condt

• The procedure is divided into the following
  steps
• Step I. A trial division is made by subtracting
  the Y register from the accumulator. The sign bit
  of the accumulator is examined and the dividend
  (accumulator) is restored by adding the divisor
  to the result of the subtraction. If the above
  sign bit is 1, the process of division is
  completed, if it is 0, the process is continued.

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Description of the division procedure condt

• Step II. The leftmost 1 bit in the divisor is
  aligned with the leftmost 1 bit in the dividend
  by shifting the divisor left and recording the
  number of shifts required to make this alignment.
  That number of shifts plus 1 is the value of the
  parameter p applied in the next step.
• Step III. The contents of the Y register is
  subtracted from the accumulator (operation
  performed in 2s complement code, the result
  replaces the contents of the accumulator). There
  are two possible cases.
• a) A new contents of the accumulator represents a
  negative number i.e. its sign bit is 1. Therefore
  the previous contents of the accumulator is
  restored by adding to it the contents of the Y
  register and the long register XB is shifted
  left one place putting 0 is as the rightmost bit
  of XB.
• b) A new contents of the accumulator represents a
  non negative number i.e. its sign bit is 0. In
  that case the long register XB is shifted left
  one place putting 1 as the rightmost bit of XB.
• The step III is repeated p times.
• Step IV. The contents of the accumulator is
  shifted right p times.

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Examples
a)
c)
b)
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Example a)
quotient 102 remainder 02 .
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Example b)
quotient 02 remainder 1102 .
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Example c)
quotient 1012 remainder 12 .