Project Overview

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High speed digital systems laboratory
Final Presentation
Project Name Serial Communication
Analyzer Presenter Name Igal Kogan
Alexander Rekhelis Instructor
Hen Broodney Semester
Winter-Spring 2001/2
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Project Goals
High speed digital systems laboratory

• Implementation of testing and debugging device
  for multipurpose serial communication protocol
  RS-232 and DSP serial communication protocol
  McBSP.
• Both protocols are implemented in Altera FPGA.
  Also PCI Interface protocol, that implemented in
  PCI MegaCore, is managed by Altera FPGA.
• The design is based on Altera Flex PCI
  Development Kit and the external devices will
  connect through bridges that are specially
  designed as RS-232 and McBSP protocols buffers.

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Abstract
High speed digital systems laboratory

• The device will collect and manage the data in
  several ways
• 1) As data buffer it will transfer the data
  from the
• input device to the output device through
  constant data collect.
• 2) As communication analyzer it will read the
  data
• from input, send it to PC through PCI
  Bus for
• processing, and according to user commands will
• send the updated data to output.
• Note Since the communication is bi-directional,
  input and output devices can be switched
  constantly.

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Abstract (cont.)
High speed digital systems laboratory
Serial Communication Analyzer and Device
Controller
RS-232
RS-232
McBSP
McBSP
Additional External Devices
Additional External Devices
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Highlights of RS232 protocol
High speed digital systems laboratory

• RS-232 is an electrical interface standard
  between Data Terminal Equipment (DTE) and Data
  Circuit-Terminating Equipment (DCE) such as
  modems, PALM, mouse and so.
• RS-232 is used for asynchronous data transfer as
  well as synchronous links.
• It appears under different incarnations such as
  RS-232C, RS-232D, V.24, V.28 or V.10 but
  essentially all these interfaces are
  interoperable.

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High speed digital systems laboratory
PC Com Port - EIA-574 RS-232 pin out DB-9 pin
used for Asynchronous Data
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High speed digital systems laboratory
One byte of asynchronous data
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Highlights of McBSP protocol
High speed digital systems laboratory

• Full-duplex communication
• Double-buffered data registers, which allow a
  continuous data stream
• Independent framing and clocking for receive and
  transmit
• Direct interface to industry-standard analog
  interface chips (AICs), and other serially
  connected analog-to-digital (A/D) and
  digital-to-analog (D/A) devices
• External shift clock or an internal, programmable
  frequency shift clock for data transfer
• Autobuffering capability through the 5-channel
  DMA controller.

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McBSP Interface Signals
High speed digital systems laboratory

• Pin I/O/Z Description
• CLKR I/O/Z Receive clock
• CLKX I/O/Z Transmit clock
• CLKS I External clock
• DR I Received serial data
• DX O/Z Transmitted serial data
• FSR I/O/Z Receive frame synchronization
• FSX I/O/Z Transmit frame synchronization

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McBSP Basic Definitions Frame
High speed digital systems laboratory
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High speed digital systems laboratory
PCI Core
PCI Bus
Local Bus
????? ?-PCI Core ??????? ??????, ??? ????? ??
???? Altera. ?????? ????? ??? ?-PCI Bus ????
Control Logic Block.
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Software (Hardware)
High speed digital systems laboratory

• RS232 protocol implementation
• The communication can be handled at 1200, 2400,
  4800, 9600, 19200, 38400, 57600, 115200 baud
  rate (can be easily increased till the maximum of
  16 Mbps).
• McBSP protocol implementation
• The communication can be handled at 128906,
  257812, 515625, 1031250, 2062500, 4125000,
  8250000, 16500000 baud rate.
• The communication rate, analyzing conditions and
  test options can be determined through User
  Interface.

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High speed digital systems laboratory
Altera PCI Development Board
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High speed digital systems laboratory
Technical Specification
1) Interface voltages 1.1) RS-232 0 -gt
3v 15v 1 -gt
-3v -15v 1.2) McBSP 0 -gt 0v
1 -gt 3.3v 2)
Communication rates 3.1) RS-232 up to
115200 bps 3.2) McBSP up to 16.5 Mbps
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High speed digital systems laboratory
Technical Specification (cont.)
3) Loopback connectivity test. 4) Communication
reliability tests 4.1) Parity checks.
4.2) CRC tests without acknowledge . 4.3)
CRC tests with acknowledge. 5) Build in debug
test (BIT).
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RS-232 pin out (addition)
High speed digital systems laboratory
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McBSP pin out (addition)
High speed digital systems laboratory
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Additional boards
High speed digital systems laboratory
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Additional boards
High speed digital systems laboratory
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DSK board for checking McBSP
High speed digital systems laboratory
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System Block Diagram
High speed digital systems laboratory
RS-232 Communication Device
RS-232 Communication Device
Altera Flex PCI Board
McBSP Communication Device
McBSP Communication Device
PC
WinDriver
GUI
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System modules diagram (FPGA)
High speed digital systems laboratory
RS-232 Protocol
RS-232 Protocol
Device Controller
McBSP Protocol
McBSP Protocol
I/O Device
I/O Device
PCI MegaCore
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FPGA design milestones
High speed digital systems laboratory

• PCI Core implemented in 32 bit target mode.
  Supports I/O read/write, memory read/write and
  configuration read/write.
• Up to six base address registers (BARs) with
  adjustable memory size and type.
• Main clock frequency supplied from PCI Bus is
  33MHz.

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FPGA design milestones (cont.)
High speed digital systems laboratory

• Local side application includes implementation
  of
• a) Interface Unit between PCI Core Local Bus and
  Device I/O Controller. Translation from Local
  Bus to internal address bus and data bus with
  appropriate controls.
• b) Device I/O Controller is a generic memory
  mapping block. Allocated memory range divided
  into three categories I/O, Command Registers
  and Status Registers. In current configuration
  of the Device I/O Controller there is allocation
  for 32 I/O Blocks, 16 Command Registers and 16
  Status Registers.

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FPGA design milestones (cont.)
High speed digital systems laboratory

• c) Peripheral Blocks
• Two RS232 transmit/receive I/O blocks
• Two McBSP transmit/receive I/O blocks
• Each I/O Block has storage capabilities of 256
  Bytes for transmit and 1KByte for receive.
• Optional I/O blocks with different purposes can
  be connected to Device I/O Controller according
  to the memory mapping.

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Hardware Development Tools
High speed digital systems laboratory

• Design with HDL Designer
• Simulation with Modelsim
• Synthesis with Leonardo Spectrum
• P R with MaxPlusII

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High speed digital systems laboratory
R E L I A B I L I T Y T E S T S
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High speed digital systems laboratory
Reliability Tests
1) Checking our side this is check for our
hardware
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High speed digital systems laboratory
Example RS-232 loopback connections
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High speed digital systems laboratory
Example McBSP loopback connections
CLKXCLKR
FSXFSR
McBSP
DXDR
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High speed digital systems laboratory
Reliability Tests (cont.)
2) Communication device closing loopback this
test checking all hardware.
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High speed digital systems laboratory
Reliability Tests (cont.)
3) Analyzer closing loopback this is good
visual test for all our design.
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High speed digital systems laboratory
Reliability Tests (cont.)
4) Parity check.
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High speed digital systems laboratory
Reliability Tests (cont.)
5) CRC Cyclic Redundancy Check (without ack)
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High speed digital systems laboratory
Reliability Tests (cont.)
6) CRC Cyclic Redundancy Check (with ack)
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High speed digital systems laboratory
Testing of the protocols (RS-232)
Terminal
Our side
GUI
Palm Example
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Project milestones
High speed digital systems laboratory
???? ?-PCI Core, ?????? ?????? ?????? ???? ?????
???? ???? ??? ?????? ?????? .
????? ????? ??????? RS-232 ?- McBSP .
????? ???????? RS232 ?-VHDL.
????? ????? ?????? ????? ?????? ?? ??????? ??????
???????.
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High speed digital systems laboratory
Project milestones
????? ???????? McBSP ?-VHDL ??????? ?- PCI Core.
????? GUI , ????? ?????? ???? ?????? ????? ?????
Windows ?- Driver ??????.
????? ???? ?? ??? ?????? ?????, ????? ??????
?????? ?????? ?? ??????? ??????? ???????????
?????? .
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Next generation proposal
High speed digital systems laboratory

• Additional synchronous and asynchronous
  communication protocols based on the developed
  platform PCI Core and Device I/O Controller.
• Up to 28 multipurpose I/O blocks can be added
  with no major changes in current design.
• Upgrade PCI Core to 66 MHz which will
  automatically increase McBSP baud rate up to
• 33 Mbps.

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Problems Solutions
High speed digital systems laboratory

• The main problem was lack of PLLs in the FPGA
  witch resulted in considerable skew in
  distributed clock over the FPGA area. In order to
  compensate the skew additional pipeline stages
  were inserted in different areas.
• Because of the fast McBSP communication, special
  communication cables and connectors must be
  prepared in order to minimize terminations and
  match impedances. Also ground layer need to be
  connected.

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Problems Solutions
High speed digital systems laboratory

• Alteras development kit datasheet has many
  mistakes in pinout.
• A lot of time and energy wasted to find these
  errors.

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High speed digital systems laboratory
Serial Communication Analyzer

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• ???