Digital Logic Design

1
Digital Logic Design

• Lecture 10
• University of Tehran

2
Outline

• More Examples on Realizing Functions Using
  Multiplexer
• Other Applications for Multiplexer
• Comparator
• Full Adder

3
More Examples on Realizing Functions Using
Multiplexer

• Last session we saw how to realize a switching
  function using a KM by relating the MUXs inputs
  to the columns of the KM. We will now do the
  same only this time using the KMs rows.
  Consider for instance the following KM

4
More Examples on Realizing Functions Using
Multiplexer (continued)

• In the last design a lot of glue logic has been
  used alongside the MUX package. We can resolve
  this problem if we use an 8-to-1 MUX instead

5
Other Applications for Multiplexer

• Another application for multiplexers is the
  transition of data between multiple sources and
  destinations
• In the above figure, suppose each source has a 4
  bit output.

6
Other Applications for Multiplexer (continued)

• One way to solve this problem could be to simply
  use one quad 4-to-1 multiplexer behind each Di
  with which each source can easily send data to
  any required destination at one time. One
  problem with this approach is that it leaves us
  with a lot of wiring, and also we will not have
  much ability in increasing the number of sources
  as all of our multiplexers will have to be
  changed.

7
Other Applications for Multiplexer (continued)

• Note The structure used in between the MUX and
  the destinations is called a bus.

8
Other Applications for Multiplexer (continued)

• A better solution to the problem is to use three
  state buffers on the output of each source with
  a common control line for all buffers relating to
  a particular source. Bye doing this only one
  source will have the ability to drive a
  particular destination at any instance of time.
  To select which source will have this ability is
  done by the use of a decoder (that can be
  initially selected larger to support a larger
  number of source that may be used in the future).
  The figures shown in the next slide, shows this
  design.

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Other Applications for Multiplexer (continued)
10
Other Applications for Multiplexer (continued)

• Again another solution for the problem that is
  very difficult to implement on a board is

11
Comparator

• To test the equality of two numbers the following
  circuit can be used (two 4 bit numbers)

12
Comparator (continued)

• The above circuit is very straightforward to
  understand considering what an XNOR gate does.
  The following circuit tests the inequality agtb,
  by first testing to see whether a3 is 1 and b3 is
  0 and doing the same test for lower bits if these
  bits are equal.

13
Comparator (continued)

• The 7485 is a standard comparator package with
  the following attributes if (AgtB) lt0,
  eq0, gt1 if (AltB) lt1, eq0, gt0 if
  (AB) ltl, eqe, gtg
  
• Quote The three l, e and g inputs are used when
  cascading.

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Comparator (continued)

• Let us now cascade four of the 7485 to construct
  a 16 bit comparator.

15
Comparator (continued)

• This comparator will first compare the 4 most
  significant bits of the two inputs, unless they
  are equal the result can be found in this first
  stage as a is less than b if its 4 MSB are
  smaller and is greater if the 4 MSB are larger.
  If these 4 MSB of the two numbers turn out to be
  equal, the comparator will recursively do the
  same comparison on less significant bits four by
  four.

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Comparator (continued)

• The comparators we have seen so far have been
  magnitude comparators, that is they only work
  correctly when their inputs are unsigned numbers.
  To be able to use the same comparators for 2s
  complement numbers, some glue logic needs to be
  used which is

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Comparator (continued)

• Lets design a maximum finder using a comparator
  and a MUX
  

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Full Adder

• Last session we saw how to implement a full adder
  using a MUX, continuing our discussion of
  arithmetic units we will now see a full adder
  realization with discrete gates.
  

19
Full Adder (continued)
20
Full Adder (continued)

• The logic diagram is

21
Full Adder (continued)

• The figure shown in the last slide, shows how to
  realize a 1 bit full adder, for a 4 bit full
  adder rippling the carry through each stage we
  may have
• The above adder is called Pseudo Parallel or
  Ripple Carry adder.

22
Full Adder (continued)

• The last design can also be used to subtract two
  4 bit numbers, considering how subtraction of 2s
  complement numbers is done in practice. All we
  have to do is complementing the bits of b and
  setting the first stages carry to 1.