CENG 241 Digital Design 1 Lecture 11

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CENG 241Digital Design 1Lecture 11

• Amirali Baniasadi
• amirali_at_ece.uvic.ca

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This Lecture

• Review of last lecture Analysis
• Chapter 5 State Reduction, Design Procedure

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Analysis of Clocked Sequential Circuits

• Analysis Obtaining a table/diagram for the time
  sequence of inputs/outputs/internal states.
• Examples State Equations, State Table, State
  Diagram

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Analysis of Clocked Sequential Circuits
Example of state equation A(t1) A(t)x(t)
B(t)x(t) B(t1) A(t)x(t) A(t1)AxBx B(t1)
Ax y(t)(A(t)B(t)).x(t) (AB)x
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Example of state tables

• Present state input Next
  State Output
• A B x A
  B y
• 0 0 0 0
  0 0
• 0 0 1 0
  1 0
• 0 1 0 0
  0 1
• 0 1 1 1
  1 0
• 1 0 0 0
  0 1
• 1 0 1 1
  0 0
• 1 1 0 0
  0 1
• 1 1 1 1
  0 0

State equation A(t1) A(t)x(t)
B(t)x(t) B(t1) A(t)x(t) y(t)(A(t)B(t)).x(t
)
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Example of state tables-2nd form

• Present state Next State
  Output
• x0 x1
  x0 x1
• AB AB AB
  y y
• 00 00 01
  0 0
• 01 00 11
  1 0
• 10 00 10
  1 0
• 11 00 10
  1 0

State equation A(t1) A(t)x(t)
B(t)x(t) B(t1) A(t)x(t) y(t)(A(t)B(t)).x(t
)
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Example of state diagram
Present state Next State
Output x0
x1 x0 x1 AB
AB AB
y y 00 00
01 0 0 01
00 11
1 0 10 00
10 1 0
11 00 10
1 0
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Mealy Moore

• Mealy machine Output depends on both input
  present state
• Moore machine Output only depends on present
  state.

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Example of Mealy Machine
Present state Next State
Output x0
x1 x0 x1 AB
AB AB
y y 00 00
01 0 0 01
00 11
1 0 10 00
10 1 0
11 00 10
1 0
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Example of Moore Machine
Present state input Next State
A B x
A B 0 0
0 0 1
0 0 1
0 0 0 1
0 1 1
0 1 1
1 0 1 0
0 1 1
1 0 1
1 0 1 1
0 0 0
1 1 1
1 1
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State Reduction and Assignment

• Goal Reduce the number of states while keeping
  the external input-output requirements.
• 2m states need m flip-flops, so reducing the
  states may reduce flip-flops.
• If two states are equal, one can be removed but
  what are equal states?

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State Reduction Example
As an example consider the input sequence
below 010101110100 applied and start from
state a. State a a b c d e
f f g f g a input 0 1 0
1 0 1 1 0 1 0 0 output 0 0
0 0 0 1 1 0 1 0 0
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State Reduction Example
Present State Next State
Output x0
x1 x0 x1 a
a b 0
0 b c
d 0 0 c
a d 0
0 d e
f 0 1 e
a f 0
1 f g
f 0 1 g
a f 0
1
States e and g are equal since for each member of
the set of inputs, they give the same output and
send the circuit either to the same state or an
equivalent state.
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State Reduction Example
Present State Next State
Output x0
x1 x0 x1 a
a b 0
0 b c
d 0 0 c
a d 0
0 d e
f 0 1 e
a f 0
1 f e
f 0 1
NEW equal states d and f
Table and state diagram after the first
reduction g is removed and replaced by state e.
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State Reduction Example
Present State Next State
Output x0
x1 x0 x1 a
a b 0
0 b c
d 0 0 c
a d 0
0 d e
d 0 1 e
a d 0
1
If we apply the same sequence State a
a b c d e d d e d e a input
0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0
0
Table and state diagram after the second
reduction f is removed and replaced by state d.
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Design Procedure
First Step From the word description of the
problem derive a state diagram exampledesign a
circuit to detect three or more consecutive 1s
in a string of bits coming through an input line.
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Design steps

• 1.From word description, derive state diagram
• 2.Reduce the number of states
• 3.Assign binary values to states
• 4.Obtain the binary coded state table
• 5.Choose the type of flip-flop used
• 6.Derive the simplified flip-flop input and
  output equations
• 7.Draw the logic diagram
• steps 4 to 7can be implemented by exact
  algorithms and can be automated.
• The part of the design that is well-defined is
  referred to as synthesis.

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State Table for Sequence Decoder

• Present State Input Next State
  Output
• A B x A
  B y
• 0 0 0 0
  0 0
• 0 0 1 0
  1 0
• 0 1 0 0
  0 0
• 0 1 1 1
  0 0
• 1 0 0 0
  0 0
• 1 0 1 1
  1 0
• 1 1 0 0
  0 1
• 1 1 1 1
  1 1

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Synthesis Using D Flip-Flops
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Logic Diagram for a Sequence Detector
DA Ax Bx DB Ax Bx yAB
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Excitation Tables

• Using flip-flops other than D can be complicated.
  
• Why? Input equations for the circuit must be
  derived indirectly from the state table
• Excitation tables can help.
• Excitation tables give us the flip-flop input for
  every state transition.
• Example JK- Recall Q(t1) JQ(t) KQ(t)
• Q(t) Q(t1) J K
• 0 0 0
  X
• 0 1 1
  X
• 1 0 X
  1
• 1 1 X
  0

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Excitation Tables- T flip-flop

• Example JK- Recall Q(t1) TQ(t) TQ(t) T
  XOR Q
• Q(t) Q(t1) T
• 0 0 0
  
• 0 1 1
  
• 1 0 1
  
• 1 1 0
  

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Synthesis Using JK Flip-Flops

• Present State Input Next State
  Flip-Flop Inputs
• A B x A
  B JA KA JB
  KB
• 0 0 0 0
  0 0 x 0
  x
• 0 0 1 0
  1 0 x 1
  x
• 0 1 0 1
  0 1 x x
  1
• 0 1 1 0
  0 0 x x
  0
• 1 0 0 0
  0 x 0 0
  x
• 1 0 1 1
  1 x 0 1
  x
• 1 1 0 0
  0 x 0 x
  0
• 1 1 1 1
  1 x 1 x
  1
• We also include J, K input conditions, derived
  from the excitation table.

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Synthesis Using JK Flip-Flops
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Synthesis Using JK Flip-Flops
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Synthesis Using T Flip-Flops
Example 3-bit Binary Counter The counter counts
the clock. Clock does not appear explicitly in
the state diagram.
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Synthesis Using T Flip-Flops
Present State Next
State Flip-Flop
Inputs A2 A1 A0 A2
A1 A0 TA2 TA1
TA0 0 0 0
0 0 1
0 0 1 0 0
1 0 1 0
0 1
1 0 1 0 0
1 1 0
0 1 0 1 1
1 0 0
1 1 1 1
0 0 1 0
1 0 0
1 1 0 1
1 1 0 0
1 1 1 1 0
1 1 1
0 0
1 1 1 1 0
0 0 1
1 1
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Synthesis Using T Flip-Flops
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Synthesis Using T Flip-Flops
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Summary

• State Reduction, Synthesis
• Reading up to page 234
• Midterm 2 Thursday July 12th 2012
• HW 5 Chapter 5- 6, 9, 10,11,12,13, 16, 18
  (ignore HDL), 19 (ignore HDL) and 20. Due
  Thursday July 19th