CENG 241 Digital Design 1 Lecture 15

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CENG 241Digital Design 1Lecture 15

• Amirali Baniasadi
• amirali_at_ece.uvic.ca

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This Lecture

• Review of last lectureShift Register, Ripple
  Counter
• Chapter 6 Registers and Counters

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4-bit Register
Loads in parallel Clear Cleans the output to
all 0s.
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Register with Parallel Load
To fully synchronize the system clock signals
should arrive at the same time at all
flip-flops. Therefore we do not control the
clock by gates.
Load 1, we load data
Load 0, register content does not change
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Shift Registers
A register capable of shifting its binary
information in one or both directions is called
the shift register.
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Serial Transfer
A digital system is in the serial mode when
information is processed one bit at a time.
Serial transfer of information from A to B
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Serial Addition
Slower compared to parallel addition, but uses
less equipment.
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Universal Shift Register

• A register capable of shifting in both directions
  and loading in parallel.

Multiplexer Inputs 0 No Change 1Shift
Right 2Shift Left 3Parallel load
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Ripple Counters

• A register that goes trough a prescribed sequence
  of states is called a counter.
• There are two groups of counters Ripple counters
  and Synchronous counters.
• Ripple counters The flip-flop output triggers
  other flip-flops.
• Synchronous counters count the clock.

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Examples of Binary Ripple Counters
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BCD Ripple Counter
A BCD counter starts from 0 ends at 9.
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Logic Diagram of BCD Ripple Counter
Q1 is applied to the C inputs of Q2 and Q8
Q2 is applied to the C input of Q4
J and K are connected to either 1 or flip-flop
outputs
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Logic Diagram of BCD Ripple Counter
Verification Does the circuit follow the states?
Q1 is complemented with every count (JK1)
Q2 complements if Q1 goes from 1 to 0 and Q8 is 0
Q2 remains 0 if Q8 becomes 1
Q4 complements if Q2 goes from 1 to 0
Q8 remains 0 as long as Q2 or Q4 is 0
When Q2 and Q4 are 1, Q8 complements when Q1
goes from 1 to 0. Q8 clears and the next Q1
transition.
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Three-Decade Decimal BCD Counter
Counts from 0 to 999 When Q8 goes from 1 to 0
the next higher order decade is triggered
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4-bit Synchronous Binary Counters
A flip-flop is complemented if all lower bits are
1.
A3 A2 A1 A0 0 0 0 0
0 0 0 1 0 0
1 0 0 0 1 1
0 1 0 0 0 1
0 1 0 1 1 0 0 1
1 1 1 0 0 0
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4-bit Up-Down Binary Counters
In a down binary counter a) The least significant
bit is always complemented b) a bit is
complemented if all lower bits are 0.
Change an up counter to a down counter The AND
gates should come from the complement outputs
instead of the normal one
Up 1, Down 0 Circuit counts up since input
comes from Normal output
Up 0, Down 1 Circuit counts down since input
comes from Complemented output
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Binary Counter with Parallel Load

• Sometimes we need an initial value prior to the
  count operation.
• Initial value I3 I2 I1 I0

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Binary Counter with Parallel Load
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Count 1, Load 0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
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Binary Counter with Parallel Load
0
Count 0, Load 1
0
1
0
1
I0
I0
1
0
I0
1
I1
I1
1
1
I1
1
I2
1
1
1
I2
1
I3
1
1
I3
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BCD counter with parallel load
In part a, 1001 is detected. In part b, 1010 is
detected. In part a, LOAD is set to 1 and
effective next cycle. In part b, counter is
immediately cleared
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Other Counters Counters with unused states
Present State Next State Flip-Flop
Inputs A B C A B C
JA KA JB KB JC KC 0 0 0 0
0 1 0 X 0 X 1 X 0
0 1 0 1 0 0 X
1 X X 1 0 1 0 1 0
0 1 X X 1 0 X 1 0
0 1 0 1 X 0 0 X
1 X 1 0 1 1 1
0 X 0 1 X X 1 1 1 0
0 0 0 X 1 X 1 0
X
JAKAB JBC, KB1 JCB KC1
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Other Counters Counters with unused states
What happens if we fall in unused states? In
this case, 111 results in 000. 011 results in
100. The Counter is self-correcting.
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Other Counters Ring Counter
A ring counter is a counter with ONLY 1 flip-flop
set to 1 at any particular time, all other are
cleared.
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Other Counters Johnson Counter
A 4 flip-flop ring counter that produces 8 states
(not 4).
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Summary

• Counters Registers
• Reading up to page 269
• Reminder Homework 6-Chapter 6 problems
  6,7,11,15,18,19,23,29 and 30 Due Thursday July
  26th.