A Back-End Design Flow for Single Chip Radios - PowerPoint PPT Presentation

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A Back-End Design Flow for Single Chip Radios

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A Case for Small Row Buffers in Non-Volatile Main Memories Justin Meza* Jing Li Onur Mutlu (*Carnegie Mellon University IBM T.J. Watson Research Center) – PowerPoint PPT presentation

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Title: A Back-End Design Flow for Single Chip Radios


1
A Case for Small Row Buffers in Non-Volatile Main
Memories
Justin Meza Jing Li Onur Mutlu (Carnegie
Mellon University IBM T.J. Watson Research
Center)
1
3
Motivation / Background
Evaluation
  • DRAM devices have destructive reads and buffer
    large rows of cells to reduce cost
  • System trends reduce the amount of data accessed
    from buffer (lt10 for some 8-core systems)
  • Due to contention among many cores
  • Due to data mapping schemes
  • Buffering large rows is energy-inefficient

8-cores, DDR3-1066 simulator modified for NVM
timing and energy 31 workloads
(Relative to DRAM) PCM STT-RAM
Energy (Read/Write) 2x/100x 0.5x/1x
Latency (Read/Write) 5x/10x 1x/1x
4
Results
47/67 less main memory energy for PCM/STT-RAM
with 64B row buffer size Small rows achieve
similar performance to large rows due to low
system row locality Better performance with
similar technology parameters (STT-RAM) due to
relaxed timing constraints compared to DRAM
2
Enabling Small Row Buffers
  • Non-volatile memories (NVMs) have non-destructive
    reads
  • Leverage to reduce row buffer size
  • We examine the system-level trade-offs of
    reducing row buffer size in NVMs

Swap row buffer and column mux in NVM
datapath Read an entire NVM row, but select and
buffer only a portion of its data
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