BWRC IC Design Flow

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BWRC IC Design Flow

• Winter Retreat January 11, 2000
• Rhett Davis, Hayden So, Paul Husted, Fred Chen,
  Dejan Markovic, Kevin Camera, Brian Etscheid,
• Ben Coates, Dave Wang,
• Prof. R. W. Brodersen, Prof. Borivoje Nikolic

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CMOS density now allows complete
System-on-a-chip Solutions
Source Brodersen, ICASSP 98
Also like to add

• FPGA
• Reconfigurable Interconnect

How do we design these chips?
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Possible Single-Chip Radio Architectures

• Software Radio
• GOAL Simplify System Design Process
• Seek architectures which are flexible such that
  hardware and protocols can be designed
  independently
• APPROACH Minimize the use of dedicated logic

• Universal Radio
• GOAL Maximize Bandwidth Efficiency and Battery
  Life
• Seek architectures which perform complex
  algorithms very fast with minimal energy
• APPROACH Minimize the use of programmable logic

Why is SOC design so scary?
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A High Level View of an Industry Standard Design
Flow
source Hitachi, Prof. R. W. Brodersen
Problems with this flow

• Every step can loop to every other step
• Each step can take hours or days for a 100,000
  line description
• HDL description contains no physical information
• Different engineers handle the front-end and
  back-end design

How have semiconductor companies made this flow
work?
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A More Accurate Picture of the Standard Flow
Source IBM Semiconductor, Prof. R. Newton

• Architecture Partition the chip into functional
  units and generate bit-true test vectors to
  specify the behavior of each unitTOOLS Matlab,
  C, SPW, (VCC)FREEZE the test vectors
• Front-End Enter HDL code which matches the test
  vectorsTOOLS HDL Simulators, Design
  CompilerFREEZE the HDL code
• Back-End Create a floor-plan and tweak the tools
  until a successful mask layout is createdTOOLS
  Design Compiler, Floor-planners, Placers,
  Routers, Clock-tree generators, Physical
  Verification

How can we improve this flow?
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Our Approach

• Pursue Seamless Automation
• Formalize the concept of design flow
• Develop a tool to automate these flows (icmake)
• Develop an IC Design Flow based on a more rich
  input description
• Simulink
• Simple Floor-plan
• Develop a Rapid Prototyping Design Flow based
  on a similar description to allow exploration of
  analog RF hardware and protocols
• BEE (Greg Wright, Hayden So)

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A Formal Definition of Design Flow
A Design Flow is a directed, acyclic graph

• Each node is a step. A step has associated with
  it a file or ordered list of files
• A step with one or more outgoing edges is a
  dependency
• A step with one or more incoming edges is a
  target. Each target has associated with it a
  command to update the file(s) from the
  dependencies
• A step can contain another design flow

This framework allows us to document, automate,
and evaluate design flows
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Our Current Design Flow

• Key Concepts
• Physical Design Hierarchy Matches Logical Design
  Hierarchy
• Simple Floor-plan is maintained as a companion
  input view

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Elaboration I Mapping Simulink to Physical
Physical design hierarchy matches the logical
design hierarchy (Hayden So, bcc)
Simulink Name scr1/SCR1/Filter/Filter200_1 Simuli
nk Library Link dec_filter_lib/Filter200 Physical
Library Name dec_filter_lib Physical Cell
Name Filter200 Physical Instance Name
Filter200_1
Simulink Name scr1/SCR1 Physical Library Name
top Physical Cell Name SCR1
Simulink Name scr1/SCR1/Filter Physical Library
Name top Physical Cell Name
SCR1_Filter Physical Instance Name Filter
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Elaboration II Wires and Macros
A Macro is a Simulink Subsystem for which the
underlying hierarchy does not match the physical
hierarchy Supported Macros
Connections in Simulink correspond to Wires
(nets) in the physical design. Nets are expanded
to buses depending on the fixed-point type.
Names attached in Simulink are preserved as net
names in the physical. In addition, some Simulink
blocks correspond to nets in the physical design

• Block general layout
• Module parameterized, tiled structure
• Buffer a module with dynamically sized output
  buffers
• VHDL general synthesized block
• Stateflow converted to VHDL and synthesized
• Lookup Table converted to VHDL and synthesized

• Constant Value (connections to power rails)
• Constant Shift
• Compare to Zero (sign bit)
• Ripper (single bit)

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Example Macros

• Module(Ben Coates, Dave Wang)
• Stateflow (Kevin Camera)

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Floor-plan Merge

• With most floor-planning tools, the old
  floor-plan is thrown out if the schematic
  hierarchy is modified
• Thus, in order to facilitate automation, we have
  to start thinking in terms of merging floor-plans
  instead of creating them

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Minimized Floor-planning

• The Simulink Designer is responsible for creating
  the floor-plan in DesignPlanner with the
  following functions
• Draw Standard Cell Rows
• Align
• Distribute/Compact
• Boundary Compaction
• The floor-plan contains placement information
  only.
• Using these functions, the Simulink designer for
  our test chip (Paul Husted) was able to learn the
  tool and floor-plan 58 of a 600,000 transistor
  chip in only6 hours

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Example Floorplan
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Adding Programmable Processors

• To ensure correct functionality, the fundamental
  library and Stateflow translator were designed to
  be correct by construction, much like an
  HDL-based design
• To verify the correctness of the fundamental
  library, an EPIC simulation step was added
• In order to add programmable processors into this
  flow, we need to investigate interfaces which are
  also correct by construction

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Project Status

• icmake program working but not yet generalized
• Design Flow complete up to the route verify
  step
• All macros functional except Stateflow and Lookup
  Table
• Debugging the Fundamental Library available
  Add, Sub, Add_Sub, Reg, Reg_R, Mult, Neg, Comp,
  MUX, Rst_gen, En_gen available in fixed size
  Var_2shift, Var_3shift
• SCR1 Chip expected by March 1st, 2000
• 625,000 transistors, 516 module instances, 6
  Stateflow, 3 Lookup, 108 Subsystems, hierarchy
  depth of 5
• 2-phase, non-overlapping clocking scheme,
  full-scan
• Flow executes in 30 minutes

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Goals for Spring 2000

• Finish the current flow and chip
• Implement a minimal energy, single phase clocking
  scheme (Fred Chen, Dejan Markovic)
• Add programmable processor capability into the
  flow (Brian Etscheid)
• Add more estimation statistical reporting into
  the flow

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Summary

• Physical Hiearchy matches Logical Hierarchy
• Simulink Designers provide Floor-plan
• Design Flow seamlessly automated from Simulink
  Floor-plan