ARM7TDMI Processor

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ARM7TDMI Processor
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ARM7TDMI processor

• The ARM7TDMI processor 32-bit ??
  microprocessor? Advanced RISC machine ?? ? ??
• ARM7TDMI ? ???
• ARM7 - 32-bit Advanced RISC Machine
• T - Thumb architecture extension
• Two separate instruction sets, 32-bit ARM
  instructions and 16-bit Thumb instructions
• D - Debug extension
• M - Enhanced multiplier
• I - Embedded ICE macrocell extension
• ARMxyzTDMIEJ-S
• x???, yMMU/MPU z?? DJTAG debug M ???
• I embeddedICE Macrocell E dsp ?? J jazelle
• F VFP S synthesizible??

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ARM7TDMI Block Diagram

• ? ??? ????
• 3-? ?????
• fetch, decode, execute
• 32-bit ??? ??(core)
• 32-bit ???? ??(core)
• 37 32-bit ????
• 32-bit ARM instruction set
• 16-bit THUMB instruction set
• 32x8 Multiplier(???)
• Barrel Shifter(?? ???)

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ARM7TDMI ?? ??(1)

• ARM7TDMI ???? 2?? ?? ??(??)
• ARM ?? executes 32-bit, word aligned ARM
  instructions
• THUMB ?? execute 16-bit, halfword aligned THUMB
  instructions
• Switching state
• THUMB ?? ??
• BX ????? operand register 0? bit? ??? ??(set)
• Automatically on return from an exception (IRQ,
  FIQ, ABORT, SWI,), if the exception was entered
  with the processor in THUMB state.
• ARM ?? ??
• BX ????? operand register 0? bit? ??(clear)
• Automatically on the processor taking an
  exception. In this case, the PC is placed in the
  exception modes link register.

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????? ??? ??
??? ?? 8bit ??? (bus width) 16bit ??? (bus width) 32bit ??? (bus width)
ARM 32bit 4??? 2??? 1???
Thumb 16bit 2??? 1??? 1???
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ARM7TDMI ?? ??(2)

• ARM7TDMI 7?? ?? ??
• User (usr) ???? ARM ???? ????
• FIQ (fiq) ?? ???? ??
• IRQ (irq) ?? ???? ??
• Supervisor (svc) ????? ?? ?? ??
• Abort mode (abt) ?????? ??? ?? ??
• System (sys) ????? ?? user ??
• Undefined (und) ???? ?????? ????? ?????
• ?? ??? ?? ????? ??? ??? ?? ???
• ???? ??????? user mode?? ??
• ? ??? ????, exception, protect? ???? ??? ??
  system ??? ???.

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ARM7TDMI Registers

• ARM7TDMI ? 37? register
• 31 general-purpose 32-bit registers
• 6 status registers(CPSR, SPSR_SVC, SPSR_adt, )
• ? 37? register?? ?? ? ?? ??.(visible 16?)
• The processor state and operating mode dictate
  which registers are available to the programmer.

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ARM State Registers Set
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THUMB State Registers Set
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Relationship between ARM and THUMB state registers

• The THUMB state registers relate to the ARM state
  registers in the following way

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Program Status Registers (1/3)

• ARM7TDMI ? ?? Current Program Status Register
  (CPSR), ? 5?? exception handler? ?? Saved Program
  Status Registers (SPSRs)
• These register's functions are
• ?? ??? ??? ALU ??? ?? ??? ??
• interrupt enable/disable ??
• ????? ???? ??

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Program Status Registers (2/3)

• Condition Code Flags
• N negative/less than flag ?? ??? ????? ?? ?
• Z zero flag ????? 0? ??? ? ?
• C carry/borrow/extend flag ????/???? ? shift
  ??? ??
• V overflow ?? ? ??
• In ARM state, all instructions may be executed
  conditionally.
• In THUMB state, only the Branch instruction is
  capable of conditional execution.
• Control Bits
• The I, F, T and M40) bits will be changed when
  an exception arises. If the processor is
  operating in a privileged mode, they can also be
  manipulated by software.
• T bit
• ??????, ? ?? thumb?? ??, ?? signal? ???? ??
• CPSR? ??? ? bit? ??? ???? ??? ??? ??? ? ??.

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Program Status Registers (3/3)

• Control Bits
• Interrupt disable bits
• I ? F bit Interrupt disable bit?. Set??? ? IRQ/
  FIQ interrupt? disable???.
• Mode bits
• The M4, M3, M2, M1 and M0 bits (M40) are the
  mode bits.
• processor's operating mode? ????.
• ??? ?? ????, processor ? reset ??? ?? ????? ???.

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Exceptions (1/5)

• Exception program? halt??? ? ????? ????.
• For example to service an interrupt from a
  peripheral.
• ARM 7 ??? exception? ??? processor mode??
  exception? ???.
• ARM Exception vectors

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Exceptions (2/5)

• When handling an exception, the ARM7TDMI
• Link Register? ?? ??? ???? ??? ????.
• SPSR? ??? CPSR?? ????.
• Exception ? ?? ?? CPSR? ????.
• Exception verctor??? fetch? ?????? PC? ????.
• ???? ?? exception?? ?? ??? ???? ???? disable
  flag? set?? ??.
• THUMB ???? exception? ????, pc? exception vector?
  ?? ?? ARM mode? ????? ??? ??.
• ??? Link Register?? offset(exception vector) ??
  ??? pc? ??.
• ??? SPSR? CPSR? ??
• ???? disable flag? clear ??.(????? set?? ????)

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Exceptions (3/5)

• Reset
• When the processors Reset input is asserted
• CPSR ? Supervisor I F
• PC ? 0x00000000
• Undefined Instruction
• If an attempt is made to execute an instruction
  that is undefined
• LR_undef ? Undefined Instruction Address 4
• PC ? 0x00000004, CPSR ? Undefined I
• Return with MOVS pc, lr
• Prefetch Abort
• Instruction fetch memory abort, invalid fetched
  instruction
• LR_abt ? Aborted Instruction Address 4,
  SPSR_abt ? CPSR
• PC ? 0x0000000C, CPSR ? Abort I
• Return with SUBS pc, lr, 4

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Exceptions (4/5)

• Data Abort
• Data access memory abort, invalid data
• LR_abt ? Aborted Instruction 8, SPSR_abt ?
  CPSR
• PC ? 0x00000010, CPSR ? Abort I
• Return with SUBS pc, lr, 4 or SUBS pc, lr, 8
• Software Interrupt
• Enters Supervisor mode
• LR_svc ? SWI Address 4, SPSR_svc ? CPSR
• PC ? 0x00000008, CPSR ? Supervisor I
• Return with MOV pc, lr

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Exceptions (5/5)

• Interrupt Request
• Externally generated by asserting the processors
  IRQ input
• LR_irq ? PC - 4, SPSR_irq ? CPSR
• PC ? 0x00000018, CPSR ? Interrupt I
• Return with SUBS pc, lr, 4
• Fast Interrupt Request
• Externally generated by asserting the processors
  FIQ input
• LR_fiq ? PC - 4, SPSR_fiq ? CPSR
• PC ? 0x0000001C, CPSR ? Fast Interrupt I F
• Return with SUBS pc, lr, 4
• Handler _at_0x1C speeds up the response time

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ARM Instruction Set
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Summary
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Condition Field (1/2)

• All ARM instructions can be conditionally
  executed, which means that their execution may or
  may not take place depending on the values of
  values of the N, C, C and V flags in the CPSR
• Every instruction contains a 4-bit condition code
  field in bits 31 to 28

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Condition Field (2/2)

• 15?? condition? ??, ???? mnemonic? 2?? ???? ???.
• Assembley?? Branch ??? ?? z-flag? set??, BEQ? ??.
• B initReset
• 0xEA00000F

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Branch Instructions (1/2)

• ?? ARM Processors branch ???? condition? ?? ? ??,
  ?? ? ?? 32Mbyte?? ?? ? ? ??. (0-24bit 25?
  0x1ffffff)
• As the Program Counter (PC) is one of the
  general-purpose registers (register 15), a branch
  or jump can also be generated by writing a value
  to register 15.
• subroutine call? ?? branch? ? ????. Branch??? ??
  r14(lr)? ???? ????? ?? ???? ??.
• load ???? 4Gbyte???? ??? ?? ???? ??? ? ??.
• ???? ?? ?? ? 32bit ?? pc? ??? branch? ????.
• The ARM7TDMI processor that support the Thumb
  instruction set also support a branch instruction
  (BX) that jumps to a given address, and
  optionally switches executing Thumb instructions.

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Branch Instructions (2/2)

• List of branch instructions
• B, BL Branch, and branch with link BX
  Branch and exchange instruction set (ARM????
  Thumb??? ??)
• Examples
• B label branch unconditionally to
  label BCC label branch to label if carry flag
  is clear BEQ label branch to label if
  zero flag is set MOV PC, 0 R15 0,
  branch to location zero BL func subroutine
  call to function
• func MOV PC, LR R15R14, return to instruction
  after the BL MOV LR, PC store the address of
  the instruction after the next one into R14
  LDR PC, func load a 32-bit value into the
  program counter

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Data Processing (1/2)

• ARM? 16?? data processing instructions. ???? data
  processing instruction? 2?? operand? ???. (Move
  ?and Move ? ???operand? ???.)
• ??? register? ??? ???? ????. ( Compare ? Test???
  ??-condition code? ?????. ??? ???? ???.)
• ??? operand? ??? ?? register?, ???? shitfer
  operand?.(??? ??? register???.? ? ?? ??.)
• ALU? operand2? ???? ?? shifter?? operand? ??? ?
  ??.

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Data Processing (2/2)

• List of data processing instructions

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?? ???? (1/2)

• ARM? 2?? ??? ?????? ??.
• normal, 32-bit result
• long, 64-bit result
• ?????? ?? ???? ??? operand register? ???.
• For example)
• MUL R4, R2, R1 Set R4 to value of
  R2 multiplied by R1 MULS R4, R2, R1
  R4 R2xR1, set N and Z flags MLA R7, R8, R9,
  R3 R7 R8xR9 R3
• ????? normal ???? ???? ?? ?? ?? ???.

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?? ???? (2/2)

• 64bit? ??? ???? 4?? ?? ??? ??. (long ??)
• 2?? ?? ??? ??? ??? ???? ?? ????.
• SMULL R4, R8, R2, R3 R4 bits 0 to 31 of
  R2xR3 R8 bits 32 to 63 of R2 x
  R3UMULL R6, R8, R0, R1 R6, R8 R0 x
  R1UMLAL R5, R8, R0, R1 R5, R8 R0 x R1 R5,
  R8

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Load / Store ??? (1/2)

• Load/ store ???? 3?? ??? ??.
• load / store ??? register?? ???.
• load / store multiple register values
• swap a register value with the value of a memory
  location
• load / store ??? register?? ???
• LDR/STR, Load/Store word
• LDRB/STRB, Load/Store byte
• LDRH/STRH, Load/Store unsigned halfword
• LDRSB, Load signed byte
• LDRSH, Load signed halfword

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Load / Store ???? (2/2)

• Load and Store multiple registers
• List of load and store multiple instructions
• LDM, Load multiple
• STM, Store multiple
• STMDB SP!, R0,R4,R5,R6,LR
• Swap a register value with the value of a memory
  location
• List of semaphore instructions
• SWP, Swap
• SWPB, Swap Byte
• SWP R12, R10, R9 load R12 from
  address R9 and
  store R10 to
  address R9
• SWPB R3, R4, R8 load byte to R3
  from address R8 and
• 
  store byte from R4 to address R8

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SWI Software Interrupt

• The Software Interrupt instruction enters
  supervisor mode
• ARM??? swi? ?? ???? ???. ????? ???? ?? JTAG
  ?????? ???? ??? ????.
• Semihosting library ???

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THUMB Instruction Set
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Summary
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Thumb ??? ???? ?

• Thumb ???? ARM???? ?? ????.
• Optimized for code density.
• ???? Thumb instruction? ARM instruction
• ADD Rd, Offset8 ltgt ADDS Rd, Rd, Offset8
• Inline expansion of Thumb Instruction to ARM
  Instruction
• Real time decompression
• Thumb instructions are not actually executed on
  the core
• The core needs to know whether it is reading
  Thumb instructions or ARM instructions.
• Core has two execution states - ARM and Thumb
• Core does not have a mixed 16 and 32 bit
  instruction set.

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Thumb Instruction Set Decompression
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Branch ????

• Thumb supports four types of branch instruction
• unconditional branch gt?? 2Kbytes(211)
• conditional branch gt?? 256 bytes (28)
• List of branch instructions
• B conditional branch
• B unconditional branch
• BL Branch with link
• BX Branch and exchange instruction set

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Data Processing ????

• Thumb data-processing instruction? ARM
  data-processing instruction? ????.
• ?? Thumb data-processing instructions set the
  condition codes
• List of data-processing instructions
• ADC, Add with Carry
• ADD, Add
• AND, Logical AND
• ASR, Arithmetic shift right
• BIC, Bit clear
• CMN, Compare negative
• CMP, Compare
• EOR, Exclusive OR
• LSL, Logical shift left
• LSR, Logical shift right

• MOV, Move
• MUL, Multiply
• MVN, Move NOT
• NEG, Negate
• ORR, Logical OR
• ROR, Rotate Right
• SBC, Subtract with Carry
• SUB, Subtract
• TST, Test

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Load / Store Register ????

• Thumb??? 8??? load / store register ????
• List of load and store register instructions
• LDR Load word
• LDRB Load unsigned byte
• LDRH Load unsigned halfword
• LDRSB Load signed byte
• LDRSH Load signed halfword
• STR Store word
• STRB Store byte
• STRH Store halfword

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Load / Store ?? ????

• Thumb??? 4?? load / store ?? ???
• 2?? block copy (a load and store)
• ??? 2?? ?????? PUSH / POP ??.
• ?????? full descending stack??? ????.
• stack pointer? base register? ????.
• List of load and store multiple instructions
• LDM Load multiple
• POP Pop multiple
• PUSH Push multiple
• STM Store multiple

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ARM vs THUMB
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Code size

• Generally, routines in THUMB code are between 65
  and 70 the size of the equivalent ARM code.

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Code performances vs Memory width
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Arm Instruction Set Advantages

• All instructions are 32 bits long.
• Most instructions are executed in one single
  cycle.
• Every instructions can be conditionally executed.
• A load/store architecture
• Data processing instructions act only on
  registers
• Three operand format
• Combined ALU and shifter for high speed bit
  manipulation
• Specific memory access instructions with powerful
  auto-indexing addressing modes
• 32 bit ,16 bit and 8 bit data types
• Flexible multiple register load and store
  instructions

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Thumb Instruction Set Advantages

• All instructions are exactly 16 bits long to
  improve code density over other 32-bit
  architectures
• The Thumb architecture still uses a 32-bit core,
  with
• 32-bit address space
• 32-bit registers
• 32-bit shifter and ALU
• 32-bit memory transfer
• Gives....
• Long branch range
• Powerful arithmetic operations
• Large address space