Timing in Sequential circuits

1
Timing in Sequential circuits Stabilization
time of a latch
1
2
Assume that thl,1 tlh,1 thl,2 tlh,2 1
time unit
2
Timing in Sequential circuits Stabilization
time of a latch
Time R S Qt Qt Qt1 Qt1
1 1 0 0 0 1 1


3
Timing in Sequential circuits Stabilization
time of a latch
Time R S Qt Qt Qt1 Qt1
1 1 0 0 0 1 1
2 1 0 1 1 0 1

4
Timing in Sequential circuits Stabilization
time of a latch
Time R S Qt Qt Qt1 Qt1
1 1 0 0 0 0 0
2 1 0 0 0 1 1
3 1 0 0 1 0 1
5
Timing in Sequential circuits Stabilization
time of a latch
Time R S Qt Qt Qt1 Qt1
1 0 1 0 1 1 0
It takes time unit for the latch to stabilize
6
clock controlled latch
1-cycle time
0-cycle time
Cycle time
7
The Instability problem
input
output
Combinatorial circuit
Memory
1
Memory is updatable
CP
thl of 1
8
Solution latch is sensitive to the change in clock
Memory is updatable
CP
9
Timing in Sequential circuits Master-Slave
Flip Flop
1
2
10
Timing in Sequential circuits Master-Slave
Flip Flop
1
2
CP
Updating the FF
11
Timing in Sequential circuits Master-Slave
Flip Flop
1
2
CP
Stabilization of latch 1 and latch 2
12
Timing in Sequential circuits Edge triggered
D-Flip Flop
13
Timing in Sequential circuits Edge triggered
D-Flip Flop
14
Timing in Sequential circuits Edge triggered
D-Flip Flop
15
Timing in Sequential circuits Edge triggered
D-Flip Flop
Stabilization before change of clock
0
1
Maintain value
1
0
1
0
0
1
0
16
Timing in Sequential circuits Edge triggered
D-Flip Flop
Stabilization after change of clock
0
1
Set value to 0
1
1
0
1
1
1
0
17
Timing in Sequential circuits Edge triggered
D-Flip Flop
0
1
Set value to 0
1
1
0
1
1
Output remains the same
Input changed
1
1
18
Timing in Sequential circuits Definitions
thold time after the change of clock
that the input must not change
tsetup time before the change of
clock that the input must not change
19
Timing in Sequential circuits Definitions
CP
tpC-Q The time it takes the output to reach
its legal value from the relevant change of
clock
tpC-Q
90
FF output
tcC-Q The time that the output does not change
after the relevant change of clock
tcC-Q
20
Timing in Sequential circuits Constraints on
the timing of the circuit
What should be the constraints on the timing
characteristics of FF 1 and 2 To ensure that the
circuit works properly?
Flip Flop 1
Flip Flop 2
21
Timing in Sequential circuits Constraints on
the timing of the circuit
What should be the constraints on the timing
characteristics of FF 1 and 2 To ensure that the
circuit works properly?
Flip Flop 1
Flip Flop 2
tcC-Q,1 gt thold,2
22
Timing in Sequential circuits Analyzing a
circuit
2
1
Updating the variables in the negative edge
(decrease from 1 to 0) FF locks in positive edge
(increase from 0 to 1).
1. What is the minimal cycle time (what are the
durations of each phase)? 2. What is the maximal
delay of the circuit output? 3. What are the
conditions on the timing properties of the clock
such that the circuit will work properly?
23
Timing in Sequential circuits What is the
minimal cycle time (what are the durations of
each phase)?
Solution I
Update Variables
Lock FF
24
Timing in Sequential circuits What is the
minimal cycle time (what are the durations of
each phase)?
Solution I
tpC-Q
tsetup
tpd(1)
25
Timing in Sequential circuits What is the
minimal cycle time (what are the durations of
each phase)?
Solution II
tpd(1)
tpC-Q
tsetup
26
Timing in Sequential circuits What is the
maximal delay of the circuit output?
Solution
2
1
tpd
27
Timing in Sequential circuits What is the
maximal delay of the circuit output?
Solution
2
1
tpd tpd(2)
The relevant clock change. The FF is already
updated here
28
Timing in Sequential circuits What are the
conditions on the timing properties of the clock
such that the circuit will work properly?
Solution
29
Timing in Sequential circuits What are the
conditions on the timing properties of the clock
such that the circuit will work properly?
Solution
thold lt tcd(1) tcC-Q