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Lecture 9 Sequential Logic Prof. Sin-Min Lee Department of Computer Science 4 Basic types of Flip-Flops SR, JK, D, and T JK ff has 2 inputs, J and K need to be ... – PowerPoint PPT presentation

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Title: Lecture 9 Sequential Logic


1
Lecture 9 Sequential Logic
CS147
  • Prof. Sin-Min Lee
  • Department of Computer Science

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3
4 Basic types of Flip-Flops
  • SR, JK, D, and T
  • JK ff has 2 inputs, J and K need to be asserted
    at the same time to change the state
  • D ff has 1 input D (DATA), which sets the ff when
    D 1 and resets it when D 0
  • T ff has1 input T (Toggle), which forces the ff
    to change states when T 1
  • SR ff has 2 inputs, S (set) and R (reset) that
    set or reset the output Q when asserted

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6
Gated D-Latch
  • Ensures S and R inputs never equal to 1 at the
    same time
  • Useful in control application where setting or
    resetting a flag to some condition is needed
  • Stores bits of information
  • Constructed from a gated SR latch and a Data
    latch

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8
Analysis of Sequential Systems
  • Goal
  • Decide the timing and functional behavior from
    the implementation of a sequential system
    composed of FFs and logic gates
  • Types
  • Functional analysis
  • Timing analysis

9
Characteristic Equation of FFs
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The origin of the name for the JK flip-flop is
detailed by P. L. Lindley, a JPL engineer, in a
letter to EDN, an electronics newsletter. The
letter is dated June 13, 1968, and was published
in the August edition of the newsletter. In the
letter, Mr. Lindley explains that he heard the
story of the JK flip-flop from Dr. Eldred Nelson,
who is responsible for coining the term while
working at Hughes Aircraft. Flip-flops in use at
Hughes at the time were all of the type that came
to be known as J-K. In designing a logical
system, Dr. Nelson assigned letters to flip-flop
inputs as follows 1 A B, 2 C D, 3 E
F, 4 G H, 5 J K. Given the size of the
system that he was working on, Dr. Nelson
realized that he was going to run out of letters,
so he decided to use J and K as the set and reset
input of each flip-flop in his system (using
subscripts or somesuch to distinguish the
flip-flops), since J and K were "nice, innocuous
letters."
12
  • Dr. Montgomery Phister, Jr., an engineer under
    Dr. Nelson at Hughes, picked up the idea that J
    and K were the set and reset input for a "Hughes
    type" of flip-flop, which he then termed "J-K
    flip-flops," a name that he carried with him when
    he left for Scientific Data Systems in Santa
    Monica.

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14
Implement D Flip-flop by T Flip-flop
Q
0 1
Q
0 1
D
T
0 1
0 1
0 0
0 1
1 0
1 1
T D Q D Q D
D
T
15
Implement JK Flip-flop by D Flip-flop
Q
0 1
Q
0 1
J K
J K
D
Q
  • 0 1
  • 0 0
  • 0
  • 1 1

0 0 0 1 1 1 1 0
0 0 0 1 1 1 1 0
  • 0 1
  • 0 0
  • 0
  • 1 1

0 1
0 1
D J Q K Q
Q
J
D
K
Q
16
Implement JK Flip-flop by T Flip-flop
Q
Q
Q
0 1
0 1
J K
Q
J K
J K
T
Q
  • 0 1
  • 0 0
  • 0
  • 1 1

0 0 0 1 1 1 1 0
0 0 0 1 1 1 1 0
  • 0 0
  • 0 1
  • 1
  • 1 0

0 0 0 1 1 0 1 1
Q 0 1 Q
Q Q
0 1
T J Q K Q
Q
J
T
K
Q
17
Implement T Flip-flop by JK Flip-flop
Q
J K
T
0 1
Q Q
0 1 1 0
0 X 1 X X 1 X
0
0 0 0 1 1 0 1 1
0 1
Q
Q
T
0 1
T
0 1
X 0 X 1
0 X 1 X
0 1
0 1
K T
J T
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20
Recap - Sequential Systems
  • Example
  • Design a D FF with a JK FF and AND, OR, NOT gates

21
Sequential Systems - Cont.
D(t) 0- 1--1 -0JK
22
Sequential Systems - Cont.
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Recap - Sequential Systems
  • Example
  • Design a D FF with a JK FF and AND, OR, NOT gates

27
T J-K Flip-Flops
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31
Sequential Circuit
32
Sequential Circuit (4)
33
Sequential Circuit (6)
34
Analysis of Sequential Circuit Logic Diagrams
Figure 8.8
35
Timing Diagram for Figure 8.8 (a)
Figure 8.9
36
State Table and State Diagram for Figure 8.8 (a)
Figure 8.10
37
K-Maps for Circuit of Figure 8.8 (a)
Figure 8.11
38
Synchronous Sequential Circuit with T Flip-Flop --
Figure 8.12
39
Timing Diagram
Figure 8.13
40
State Table and State Diagram
41
K-Maps for Example
42
Example 2.Synchronous Sequential Circuit with JK
Flip-flops
43
Timing Diagram and State Table for Example 2
44
K-Maps for Example 2
45
Generating the State Table From K-maps --
Example 2
46
Example 3.Synchronous Sequential Circuit Synthesis
47
Introductory Synthesis Example -- Example 3
48
Flip-flop Input Tables -- Example 3
49
Generating the JK Flip-flop Excitation Maps
--Example 3
50
Clocked JK Flip-Flop Implementation --Example 3
51
Application Equation Method for Deriving
Excitation Equations -- Example 3
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53
Registers
  • Two independent flip-flops with clear and preset

54
Registers
  • Missing Q, preset, clocks ganged
  • Inversion bubbles cancelled, so loaded with
    rising
  • Can make 8- bit register with this
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