CHAPTER 5 Synchronous Sequential Logic

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CHAPTER 5Synchronous Sequential Logic
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Sequential Circuits
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Sequential Circuits

• There are two main types of sequential circuits
  and their classification depends on the timing of
  their signals.
• A synchronous sequential circuit is a system
  whose behavior can be defined from the knowledge
  of its signals at discrete instants of time.
• The behavior of an asynchronous sequential
  circuit depends upon the input signals at any
  instant of time and the order in which the inputs
  change.

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Sequential Circuits

• A synchronous sequential circuit employs signals
  that affect the storage elements only at discrete
  instant of time.
• Synchronization is achieved by a timing device
  called a clock generator that provides a periodic
  train of clock pulses.
• Clocked sequential circuits
• The storage elements used in clocked sequential
  circuits are called flip-flops. A flip-flop is a
  binary storage device capable of storing one bit
  of information.
• The outputs can come either from the
  combinational circuit or from the flip-flops or
  both.

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Synchronous Clocked Sequential Circuit
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Latches
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SR Latch with NAND Gates
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SR Latch with Control Input
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D Latch

• One way to eliminate the undesirable condition of
  the indeterminate state in the SR latch is to
  ensure that inputs S and R are never equal to 1
  at the same time.
• Transparency latch

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Graphic Symbols for Latches
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Flip-Flops

• The D latch with pulses in its control input is
  essentially a flip-flop that is triggered every
  time the pulse goes to the logic 1 level.
• The state transitions of the latches start as
  soon as the clock pulse changes to the logic 1
  level. The new state of a latch appears at the
  output while the pulse is still active.

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Flip-Flops

• The problem with the latch is that it responds to
  a change in the level of a clock pulse.
• The key to the proper operation of a flip-flop is
  to trigger it only during a signal transition. A
  clock pulse goes through two transitions from 0
  to 1 and the return from 1 to 0.
• The positive transition is defined as the
  positive-edge and the negative transition as the
  negative-edge.

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Clock Response in Latch and Flip-Flop
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Edge-Triggered D Flip-Flop
Negative-Edge-Triggered Flip-Flop
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Positive-Edge-Triggered Flip-Flop
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Graphic Symbol for Edge-Triggered D Flip-Flop

• Setup time, Hold Time, Propagation delay

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Setup time and Hold Time
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DFF
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JK Flip-Flop

• The J input sets the flip-flop to 1, the K input
  reset it to 0, and when both inputs are enabled,
  the output is complemented. D JQ KQ

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JKFF
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JKFF
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JKFF
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Frequency Divider
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Frequency Divider
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Frequency Divider
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T Flip-Flop

• D T ? Q TQ TQ

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Characteristic Tables and Equations

• Q(t 1) D (D Flip-Flop)
• Q(t 1) JQ KQ (JK Flip-Flop)
• Q(t 1) TQ TQ (T Flip-Flop)

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Direct Input
0
1
1
0
1
0
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A(t)x(t)
B(t)x(t)

• A(t 1) A(t)x(t)
• B(t)x(t)
• B(t 1) A(t)x(t)
• y(t) A(t) B(t)x(t)

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State Table
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State Diagram
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Flip-Flop Input Equations

• The FF input functions and the circuit output
  functions determine the combinational part of the
  sequential circuit
• DA Ax Bx
• DB Ax
• y (A B)x
• Output equations and flip-flop input equations

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DA A ? x ? y
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Analysis with JK Flip-Flops
Moore Machine
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State Diagram
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AB Ax ABx
AB
Bx
Moore Machine
x ? B
x
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Mealy Machine
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Simulation Results
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State Reduction

• Two FSMs are said to be equivalent if given any
  input sequence, starting from an identical
  initial
• state, they produce the same output sequence.
• (1) Find rows in the state table that have
  identical NS
• and O/P entries. They correspond to
  equivalent
• states. If there are no equivalent
  states, stop.
• (2) When 2 states are equivalent, one of them
  can
• be removed. Update the entries of the
  remaining
• table to reflect the change. Go to (1).

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State Reduction
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State Reduction
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State Reduction
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State Assignment
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State Assignment
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Flip-Flop Excitation Tables

• Given the state transition table, we wish to find
  the FF input conditions that will cause the
  required transitions. A tool for such a purpose
  is the excitation table, which can be derived
  from the characteristic table (or equation).
• The excitation table for the JK flip-flop has
  many dont-cares, which are more likely to result
  in simpler combinational circuits.
• Many digital systems are constructed entirely
  with JK FFs because they are the most versatile
  available.
• D FFs are appropriate for applications requiring
  transfer of data (such as shift registers) T
• FFs are good for those involving complementation
  (such as binary counters) and JK FFs are for
  general use.

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Design Procedure

• 1. Circuit behavior (function) description ?
  State diagram
• 2. Reduce the number of states if necessary
• 3. Assign binary values to the states (State
  assignment)
• 4. Obtain the binary-coded state table
• 5. Choose the type of FFs to be used
• 6. Derive the simplified flip-flop input
  equations and output equations
• 7. Draw the logic diagram

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Sequence Detector
S0 00 S1 01 S2 10 S3 11
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Maps for Sequence Detector
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Logic Diagramof Sequence Detector
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Synthesis Using JK FFs
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Maps for J and K Input Equations
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Synthesis Using T FFs

• Binary counter

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State Table for 3-Bit Counter
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Logic Diagram of 3-Bit Binary Counter
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3-Bit Binary Counter
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Maps for 3-Bit Counter
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Logic Diagram of 3-Bit Binary Counter
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Serial Binary Adder