Building a Computer

1
Building a Computer
I wonder where this goes?
MIPS Kit
2
THIS IS IT!

• Motivating Force or Inciting Incident
• This is the point in the course where the PLOT
  actually begins. We are now ready to build a
  computer.
• The ingredients are all in place, now it is time
  to build a legitimate computer. One that
  executes instructions, much the way any other
  desktop, PDA, or other computer does.

3
Review The MIPS ISA

• The MIPS instruction set as seen from a Hardware
  Perspective

R-type ALU with Reguster operands Regrd ?
Regrs op Regrt
rs
rt
immediate
001XXX
I-type ALU with constant operand Regrt ?
Regrs op SEXT(immediate)

• Instruction classes
• distinguished by types
• 3-operand ALU
• ALU w/immediate
• Loads/Stores
• Branches
• Jumps

rs
rt
immediate
10X011
I-type Load and Store Regrt ? MemRegrs
SEXT(immediate) MemRegrs SEXT(immediate)
? Regrt
rs
rt
immediate
10X011
I-type Branch Instructions if (Regrs
Regrt) PC ? PC 4 4SEXT(immediate) if
(Regrs ! Regrt) PC ? PC 4
4SEXT(immediate)
26-bit constant
00001X
J-type jump PC ? (PC 0xf0000000)
4(immediate)
4
Design Approach
Incremental Featurism
Each instruction class can be implemented using a
simple component repertoire. Well try
implementing data paths for each class
individually, and merge them (using MUXes, etc).
Steps 1. 3-Operand ALU instructions 2. ALU
w/immediate instructions 2. Load Store
Instructions 3. Jump Branch instructions 4.
Exceptions
5
A Few ALU Tweaks

• Lets review the ALU that we built a few lectures
  ago. (With a few minor additions)

A
B
5-bit ALUFN
Sub Bool Shft Math OP 0 XX 0
1 AB 1 XX 0 1
A-B X X0 1 1 0 X
X1 1 1 1 X 00
1 0 BltltA X 10 1 0
BgtgtA X 1 1 1 0 BgtgtgtA X
00 0 0 A B X 01 0
0 A B X 10 0 0 A
B X 1 1 0 0 A B
Sub
Bool
1 0
Shft
Math
1 0
R
FlagsV,C
N Flag
Z Flag
6
Instruction Fetch/Decode

• Use a counter to FETCH the next instruction
• PROGRAM COUNTER (PC)

• use PC as memory address
• add 4 to PC, load new value at end of cycle
• fetch instruction from memory
• º use some instruction fields
  directly (register numbers, 16-bit
  constant)
• º use bits lt3126gt and lt50gt to
  generate controls

PC
00

Instruction
A
Memory
32
D
4
32
32
INSTRUCTION WORD FIELDS
OP3126, FUNC50
7
3-Operand ALU Data Path
R-type ALU with Reguster operands Regrd ?
Regrs op Regrt
PC

Rt lt2016gt
Register
RA1
RA2
Rd lt1511gt
WD
WA
File
RD1
RD2
WE
WERF
32
32
A
B
ALU
ALUFN
ALUFN
WERF
32
8
Shift Instructions
R-type ALU with Register operands sll
Regrd ? Regrt (shift) shamt sllv Regrd ?
Regrt (shift) Regrs
PC

Rt lt2016gt
Rs lt2521gt
Register
RA1
RA2
Rd lt1511gt
WD
WA
File
RD1
RD2
WE
WERF
shamtlt106gt
ASEL
A
B
ALU
ALUFN
ASEL!
ALUFN
WERF
32
ASEL
9
ALU with Immediate
PC

Rt lt2016gt
BSEL
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
imm lt150gt
SEXT
BSEL
SEXT
A
B
ALU
BSEL!
BSEL
SEXT
15 14 13 12 3 2 1 0
ALUFN
...
31 30 17 16 15 14 13 12
3 2 1 0
ASEL
10
Load Instruction
rs
rt
100011
immediate
I-type Load Regrt ? MemRegrs
SEXT(immediate)
PC

Rt lt2016gt
BSEL
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
SEXT
SEXT
SEXT
A
B
ALU
Wr
WD
WDSEL
Data Memory
Wr
RD
Adr
32
ASEL
32
0 1 2
WDSEL
11
Store Instruction
rs
rt
immediate
10X011
I-type Store MemRegrs SEXT(immediate) ?
Regrt
PC

Rt lt2016gt
BSEL
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
32
No WERF!
A
B
SEXT
ALU
ASEL
12
JMP Instructions
PClt3129gtJlt250gt00
26-bit constant
00001X
J-type j PC ? (PC 0xf0000000)
4(immediate) jal PC ? (PC 0xf0000000)
4(immediate) Reg31 ? PC 4
PCSEL
0
1
2
3
4
5
6
PC

Rt lt2016gt
WASEL
Jlt250gt
0 1 2 3
Register
RA1
RA2
WD
31
WA
WA
File
27
RD1
RD2
WE
Imm lt150gt
PCSEL
A
B
SEXT
ALU
WERF
ASEL
PC4
32
13
BEQ/BNE Instructions
PClt3129gtJlt250gt00
rs
rt
10X011
immediate
BT
R-type Branch Instructions if (Regrs
Regrt) PC ? PC 4 4SEXT(immediate) if
(Regrs ! Regrt) PC ? PC 4
4SEXT(immediate)
PC

That x4 unit is trivial. Ill just wire the
input shifted over 2bit positions.
Rt lt2016gt
Jlt250gt
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
Z
x4

Why add, another adder? Couldnt we reuse the one
in the ALU? Nope, it needs to do a subtraction.
PCSEL
BT
A
B
SEXT
ALU
Z
WERF
ASEL
PC4
32
14
Jump Indirect Instructions
PClt3129gtJlt250gt00
BT
JT
R-type Jump Indirect, Jump and Link
Indirect jr PC ? Regrs jalr PC ?
Regrs, Regrd ? PC 4
PC

Rt lt2016gt
Jlt250gt
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
JT
Z

PCSEL
BT
A
B
SEXT
ALU
Z
WERF
ASEL
PC4
32
15
Loose Ends
PClt3129gtJlt250gt00
rs
rt
BT
JT
001XXX
immediate
I-type set on less than set on less than
unsigned immediate slti
if (Regrs lt SEXT(imm)) Regrt ? 1 else
Regrt ? 0 sltiu if
(Regrs lt SEXT(imm)) Regrt ? 1 else Regrt
? 0
PC

Rt lt2016gt
Reminder To evaluate (A lt B) we first
compute A-B and look at the flags. LT
N ? V LTU C
Jlt250gt
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
JT
Z
N
V
C

PCSEL
BT
A
B
SEXT
ALU
V
N
C
Z
WERF
ASEL
PC4
32
16
More Loose Ends
PClt3129gtJlt250gt00
BT
JT
R-type set on less than set on less than
unsigned slt if (Regrs
lt Regrt) Regrd ? 1 else Regrd ? 0
sltu if (Regrs lt Regrt)
Regrd ? 1 else Regrd ? 0
PC

Rt lt2016gt
Jlt250gt
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
JT
Z
N
V
C

PCSEL
BT
A
B
SEXT
ALU
V
N
C
Z
WERF
ASEL
PC4
32
17
LUI Ends
PClt3129gtJlt250gt00
rt
BT
JT
001XXX
immediate
00000
I-type Load upper immediate
lui Regrt ? Immediate ltlt 16
PC

Rt lt2016gt
Jlt250gt
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
SEXT
JT
SEXT
Z
N
V
C
shamtlt106gt

16
ASEL
2
0
1
PCSEL
BT
WASEL
A
B
SEXT
ALU
V
N
C
Z
WERF
ASEL
PC4
32
18
Reset, Interrupts, and Exceptions
FIRST, we need some way to get our machine into a
known initialstate. This doesnt mean that all
registers will be initialized, justthat well
know where to fetch the first instruction. Well
call this control input, RESET Wed also like
RECOVERABLE INTERRUPTS for FAULTS (eg, Illegal
Instruction) - CPU or SYSTEM
generated synchronous TRAPS system calls
(eg, read-a-character) - CPU generated
synchronous I/O events (eg, key struck)
- externally generated asynchronous EXCEPT
ION GOAL Interrupt running program, invoke
exception handler, return to continue execution.
These are Software notions of synchrony and
asynchrony.
(Implemented as an agreed upon Illegal
instruction)
19
Exceptions
0x80000000
PClt3129gtJlt250gt00
0x80000040
BT
JT
0x80000080
Reset PC ? 0x80000000
Bad Opcode Reg27 ? PC4 PC ? 0x80000040
IRQ Reg27 ? PC4 PC ?
0x80000080
PC

Rt lt2016gt
Jlt250gt
Register
RA1
RA2
WD
WA
WA
File
RD1
RD2
WE
Imm lt150gt
RESET
SEXT
JT
SEXT
Z
N
V
C
IRQ

PCSEL
BT
WASEL
A
B
SEXT
ALU
V
N
C
Z
WERF
ASEL
LSEL
PC4
32
20
MIPS Our Final Version
This is a complete 32-bit processor. Although
designed in one class lecture,it executes the
majority of theMIPS R2000 instruction set.

• Executes one instruction per clock
• All thats left is the control logic
  design

21
MIPS Control

• The control unit can be built as a large ROM

Instruction R E S E T I R Q Z N V C P C S E L SEXT WASEL WDSEL ALUFN Sub Bool Shft Math ALUFN Sub Bool Shft Math ALUFN Sub Bool Shft Math ALUFN Sub Bool Shft Math WR WERF A S E L BSEL
X 1 X X X X X 4 0 0 0 0 00 0 0 0 0 0 0
X 0 1 X X X X 6 0 3 0 0 00 0 0 0 0 0 0
add 0 0 X X X X 0 0 0 1 0 00 0 1 0 1 0 0
sll
andi
lw
sw
beq