Multioperand Addition

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Lecture 6
Multioperand Addition
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Required Reading
Behrooz Parhami, Computer Arithmetic Algorithms
and Hardware Design
Chapter 8, Multioperand Addition Note errata
at http//www.ece.ucsb.edu/parhami/text_comp_ari
t_1ed.htmerrors
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Recommended Reading
J-P. Deschamps, G. Bioul, G. Sutter, Synthesis
of Arithmetic Circuits FPGA, ASIC and Embedded
Systems
Chapter 11.1.12 Multioperand Adders
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Applications of multioperand addition
Inner product
Multiplication
n-1
n-1
s ? x(i) y(i) ?
pax
p(i)
i0
i0
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Number of bits of the result
n-1
S ? x(i)
x(i) ?0..2k-1
i0
Smax n (2k-1)
Smin 0
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Serial implementation of multioperand addition
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Adding 7 numbers in the binary tree of adders
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Ripple-carry adders at levels i and i1
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Example Adding 8 3-bit numbers
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Ripple-Carry Carry Propagate Adder (CPA)
a2
b2
a1
b1
a0
b0
an-1
bn-1
c0
c3
c2
c1
cn
cn-1
. . .
FA
FA
FA
FA
s2
s1
s0
sn-1
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Carry Save Adder (CSA)
c0
c1
c2
cn-1
b0
b1
b2
bn-1
a0
a1
a2
an-1
. . .
FA
FA
FA
FA
c2
c3
s2
s1
c1
s0
s3
sn-1
cn
cn-1
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A Ripple-Carry vs. Carry-Save Adder
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Operation of a Carry Save Adder (CSA)
Example
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x y z
0 1 0 1 0 1 1 0 1 1 1 0 1 1 1
s c
0 0 1 1 0 1 1 0 1 1
xyz s c
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Carry propagate and carry-save adders in dot
notation
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Specifying full- and half-adder blocks in dot
notation
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Carry-save adder for four operands
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Carry-save adder for four operands
s0
s3
s2
s1
c2
c1
c3
c4
s0


s1
s2
s3


c1
c2
c3
c4




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Carry-save adder for four operands
y
z
w
x
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4
4
4
CSA
s
c
CSA
s
c
CPA
S
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Carry-save adder for six operands
Implementation of one-bit slice
CSA tree
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Tree of carry save adders reducing seven numbers
to two
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Addition of seven six-bit numbers in dot notation
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Adding seven k-bit numbers block diagram
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Relationship Between Number of Inputs and Tree
Height
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Parameters of tree carry-save adders (1)
Latency
LatencyCSA h(n) ? TFA LatencyCPA(k,
n)
Tree height for n operands
Widths
Component Adders
typically close to k bits
k .. k log2 n
CSA
? k log2 n
CPA
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Parameters of tree carry-save adders (2)
Maximum number of inputs that can be reduced to
two by an h-level tree, n(h)
n(0) 2
n(h) n(h-1)
n(1) 3 n(2) 4 n(3) 6
n(4) 9 n(5) 13 n(6) 19
2 ( )h-1 lt n(h) ? 2 ( )h
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Parameters of tree carry-save adders (3)
Smallest height of the tree carry save adder for
n operands, h(n)

h(n) 1 h( )
2
n
3
h(2) 0
h(n) ? log ( )
n
3
2
2
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Wallace vs. Dadda Trees (1)
Wallace trees

• Reduce the size of the final Carry Propagate
  Adder (CPA)
• Optimum from the point of view of speed

Dadda trees

• Reduce the cost of the carry save tree
• Optimum (among the CSA trees) from the point of
• view of area

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Wallace vs. Dadda Trees (2)

• Wallace reduces number of operands at earliest
  opportunity
• Goal of this is to have smallest number of bits
  for CPA adder
• However, sometimes having a few bits longer CPA
  adder does not affect the propagation delay
  significantly (i.e. carry-lookahead)
• Dadda seeks to reduce the number of FA and HA
  units
• May be at the cost of a slightly larger final CPA

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Wallace Tree
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Dadda Tree
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5-to-3 Parallel Counter
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a b c d e
0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1
s0 s1 s2
0 1 1 1 0 0 1 1 0 0 1 0 0 1 1
abcde s0s1s2
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Implementation of 1-bit of 5-to-3 parallel
counter using single CLB slice of a Virtex FPGA
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Carry Save Adder vs. 5-to-3 Parallel Counter
a
b
c
d
e
w
w
w
w
w
CSA
CSA
CSA
CPA
w
yabcde mod 2w
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Generalized Parallel Counters
Multicolumn reduction
(5, 5 4)-counter
Generalized parallel counter Parallel
compressor
(2, 3 3)-counter
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