Fast Multioperand Addition using 7:3 Compressors

1
Fast Multi-operand Addition using 73
Compressors

• Speed and Cost Comparison

2
Terminology

• xy/z
• x the number of inputs
• y the number of outputs
• z the number of gate delays
• Some papers do not count carries in their numbers
• Example
• A standard full adder as shown below is a
  32/3-compressor.

3
43/3-Compressor

• There are papers which outline use of 43, 53,
  or 63 compressors.
• This falls short as any compressor that accepts lt
  8 inputs will have a 3-bit output.
• Thus, a 73 compressor is optimal.

4
73-Compressor Strategy

• Split the compressor into a 43 and a 32
  compressor.
• Determine the number of 1's in the first 4
  inputs.
• Use that value to determine the final value based
  on the 32 output
• This means we need to compute the number of 1's
  in the 43 compressor input.
• TC Decoder

5
TC0 Computation

• Easiest way to compute this value is to add 2 OR
  gates and a NOR gate such that if all inputs are
  0 then the output of the final NOR gate would be
  1
• However, during the computation of TC2 it became
  necessary to know if both of 2 sets of inputs
  were false by signifying a true

6
TC1 Computation

• If the output sum of this circuit is true then we
  have either TC3 or TC1 equal to true.
• But, if TC3 is true, then one of the 2 AND gates
  connected to the 2 input pairs must also be true.
• If they are both false, then TC3 must be false
  and TC1 is true.

7
TC2 Computation

• 3 Cases
• A and B are both true but C and D are both false.
• C and D are both true but A and B are both false.
• Only one of A or B is true and only one of C or D
  is true
• The choice to use NOR gates in the computation of
  TC0 is apparent since we can use these same gates
  for this computation as well.

8
TC3 Computation

• If the sum is true and either pair of inputs is
  also both true then TC3 is true.
• Computation is thus similar to TC1
• Takes advantage of sum value already computed in
  the 4-bit adder
• Only a single XOR gate and a single AND gate are
  added.

9
TC4 Computation

• Both pairs of inputs must be all 1's
• Requires no additional gates to the 4-bit adder
  since we are using the C2 value.

10
Combined TC Decoder

• No Gate delays are added to achieve this!!!
• TC Decoder still has all of the outputs of the
  original 4-bit adder allowing us to use them for
  the 7-bit computations.

11
7-bit Computations

• TC Decoder allows us to determine the final carry
  bits with 7 inputs
• Sum is the sum of the 2 adders
• The TC Table shows how the TC Decoder combined
  with the Full Adder gives us the proper carry
  bits.
• Boolean Equations

12
73/6-Compressor
13
73/5-Compressor
14
32/3 7 Input Wallace Tree

• Use outputs of one level of the tree as inputs to
  the next level
• No carries are computed since we save them until
  the next stage
• Final Stage is done with standard carry
  propagation adder.

15
73/5 7 Input Pamplin Tree

• We use CSA-73/5 adders to reduce to 3.
• Next to last stage is done with standard full
  adder.
• Final stage is done with carry propagation adder.

16
Performance Comparison
3/23 - Wallace Tree
7/35 - Pamplin Tree
17
Cost Comparison
3/23 - Wallace Tree
7/35 - Pamplin Tree
18
Total Gate Comparison

• CSA-73/5 requires ¼ the number of compressors
  than CSA-32/3
• 73/5 compressor requires 8 times more logic
  gates than the 32/3 compressor.
• Actual difference in cost is a factor of 2.

19
Conclusion

• A new combinatorial circuit compressor is
  designed that will take as input 7 numbers and
  add them while also outputting 2 carry bits.
• This adder can be created with a gate delay time
  of 5 as opposed to the gate delay of 3 for the
  standard full adder.
• This new compressor allows for the creation of
  arbitrary word length adders that can add a large
  number of operands more quickly than the
  traditional full adder.
• By configuring this adder for use as a carry save
  adder in a tree structure, computation of large
  numbers of operands can be reduced by an average
  of 23.5.
• This performance improvement comes at a cost of
  approximately twice the number of logic gates as
  the traditional Wallace Tree implementation.

20
Future Work

• The actual transistor implementation of the new
  73/5-compressor has not been designed.
• It is very likely that the overall delay cost can
  be reduced in terms of transistor delay since a
  large number of gates can take advantage of
  pass-logic implementations.
• In addition, actual creation of a VLSI chip to
  perform multi-operand addition and subsequent
  input simulations could be done to verify the
  mathematical results presented in this paper.