Multioperand Decimal Addition

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Multioperand Decimal Addition

• Kenney, R.D. Schulte, M.J, Multioperand decimal
  addition, IEEE Computer society Annual
  Symposium, pp. 251 - 253 Feb, 2004.
• Advisor Dr . Shu-Chung Yi
• Author Shi-Xun Chang

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Outline

• Introduction
• Speculative Adders
• Non-Speculative Adders
• Synthesis Results

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Introduction

• Recently, support for decimal arithmetic has
  received increased attention due to the growing
  importance of financial, commercial, and
  Internet-based applications, which cannot
  tolerate errors from converting between decimal
  and binary formats. Since many decimal numbers,
  such as 0.1, cannot be exactly represented in
  binary, these applications often store data in
  decimal format and process data using decimal
  arithmetic software eliminates conversion errors.

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Speculative Adders

• In BCD addition, a correction of six must be
  added if a digit sum is greater than nine to skip
  over the invalid BCD digits. One technique we
  developed, called Single Correction Speculation
  (SCS).

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Speculative Adders

• The SCS adders speculate the sum to be less than
  or equal to nine for the first addition and add a
  correction of zero with the first two operands.
  

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Speculative Adders

• With the remaining additions, the carry-out of
  the previous digit-wide carry-save addition,
  , is used to decide whether to add or
  .

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Double Correction Speculation Adders

• DCS removes the multiplexers that select between
  and from the critical path , since
  the correction for two addition ahead is selected
  while the next addition is performed.

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Double Correction Speculation Adders

• It also removes one of the 6 logic blocks
  because
• Is always used. The only negative consequence of
  DCS is that determining the final speculation
  correction is slightly more complex.

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Non-Speculative Adders

• The NS uses a carry-save adder tree to sum digits
  
• to . The result is a 5-bit binary sum and
  three intermediate carry-outs. The 5-bit binary
  sum and the three carry-outs are fed into carry
  and correction generation logic.

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Synthesis Results

• All of the multioperand adders designed are
  synthesized using the same parameters. The adders
  are synthesized using the LSI Logic 0.18 micro
  CMOS standard cell library. The number of input
  operands for the constructed adders ranges from
  four to sixteen operands.

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Synthesis Results

• Though area for the NS and SCS adders are
  similar, DCS adders have the lowest average area
  of the three.

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Thanks for your attention !