Experiment 1 Lab 4 Outline

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• Experiment 1 Lab 4 Outline
• Presentation
• Using A Brief Look at Semiconductor Technology
• Component selection for a new chip and a new PCB
• Semiconductor technology overview
• Gates, switches and digital electronic circuits
• Complementary Metal Oxide Semiconductor (CMOS)
  overview
• Transistor-Transistor Logic (TTL) overview
• Using Term Project (pages 20 - 21)
• Analysis of the term project
• Digital Systems
• Analysis of Block 3 of the term project
• Using Term Project Design Checks
• Digital Design Conventions
• Individual work
• Experiment 1 is over three weeks Labs 3, 4 and
  5
• Develop a 4-bit 2-to-1 MUX of Block 2
• By using Handout 3 distributed in class

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Todays work

• Presentation
• Xilinx Project Development Steps
• Develop the schematic
• Design the schematic
• Place the components and wires
• Do a schematic check
• Test the schematic via logic simulations
• Do a Xilinx IMPLEMENTATION
• It maps the components to the CLBs of the chip
• Do timing simulations to test the schematic
• It generates the bit file
• Download the bit file to the FPGA and test the
  design on the board
• It programs the chip

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• Developing a digital product
• A new chip
• Which gates FFs and how many is determined by
• Available components of technology chosen
• Besides the major operations and speed, cost,
  power, etc. design goals of the digital product
• FPGAs are used to test the new chip
• A new PCB
• Which chips and how many is determined by
• Available chips of technology chosen
• Besides the major operations and speed, cost,
  power, etc. design goals of the digital product

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• Developing a digital product
• A new chip
• We will try to use high density components as
  much as possible
• We will try not to use low-density components
  (gates and flip-flops)
• We will work on chip design in the classroom and
  in the lab
• Lectures, homework assignments, exams and labs

6

• CS2204 Components
• Available components for a new chip

Generic components Lectures, homework, exams
Xilinx components Labs
Gates
Flip-flops
Popular digital circuits
Gates
Flip-flops
Popular digital circuits
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
AND OR NOT NAND NOR
D JK T SR
AND OR NOT NAND NOR
D T JK
High-density components
To save time, space, power. weight,
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• CS2204 Components
• Available components for a new chip

Xilinx components Labs
Generic components Lectures, homework, exams
Gates
Flip-flops
Popular digital circuits
Gates
Flip-flops
Popular digital circuits
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
AND OR NOT NAND NOR
D T JK
AND OR NOT NAND NOR
D JK T SR
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
High-density components
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• Developing a digital product
• A new PCB
• We will try to use high density chips (MSI, LSI,
  VLSI, ULSI) as much as possible
• We will try not to use low-density chips (SSI)
• We will work on PCB design in the classroom
• Lectures, homework assignments and exams

9

• CS2204 components
• Available chips for a new PCB

Generic chips Lectures, homework, exams
TTL LS chips Lectures, homework, exams
Gates
Flip-flops
Popular digital circuits
Gates
Flip-flops
Popular digital circuits
AND OR NOT NAND NOR
D JK T SR
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
AND OR NOT NAND NOR
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
D JK
High-density chips
To save time, space, power. weight,
10

• CS2204 components
• Available chips for a new PCB

TTL LS chips Lectures, homework, exams
Generic chips Lectures, homework, exams
Gates
Flip-flops
Popular digital circuits
Gates
Flip-flops
Popular digital circuits
AND OR NOT NAND NOR
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
D JK
ADDer Comparator Multiplexer DeMux Decoder Encoder
ALU Counter Register
AND OR NOT NAND NOR
D JK T SR
MSI, LSI chips
High-density chips
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• Digital circuits consist of gates and FFs
• FFs consist of gates
• Digital circuits consist of gates !
• Gates are on chips !
• Chips are on PCBs

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• Gates are implemented by electronic components
• Transistors, resistors, diodes, capacitors,

74LS00 Quad 2-input TTL NAND Gate chip
From ON Semiconductor LS TTL Data Manual
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• Most Common Voltages for Logic Values
• Logic 1 is 5v
• Logic 0 is 0v
• The terminology
• 5v ? VCC
• 0v ? GND (Ground)
• Xilinx Devices for voltages

VCC and GND are on the Xilinx component list
CMOS 2-input NAND gate implementation via
electronic components
2-input NAND gate
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• Transistors are the Main Electronic Component
• Transistors are used as switches to implement
  gates
• A switch is open or closed based on the control
  input value
• Open when control is 0
• Closed when control is 1
• The speed of switches determines the speed of the
  electronic circuit, therefore, the gate

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• Implementing AND gates
• Implemented by two switches connected in series

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• Implementing OR gates
• Implemented by two switches connected in parallel

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• Implementing NOT gates
• Implemented by one switch

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• 2-to-1 MUX Implementation

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• The Gate Implementation
• Implementing gates is more complex than just
  connecting switches (transistors) in
  series/parallel
• A 2-input NAND gate implementation
• Resistors, diodes, etc. are used for reliable
  operation with TTL technology
• Five transistors Q1 Q5, six diodes D1 D6
  and seven resistors
• Multiple transistors are used for reliable
  operation with CMOS technology
• A 2-input NAND gate implementation
• Four transistors

CMOS 2-input NAND gate implementation via
electronic components
TTL 2-input NAND gate ON Semiconductor LS TTL
Data Manual
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• Electronic Components on the Chip
• All electronic components are placed in the die
  area

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• Die Fabrication Today
• Dice for the same chip type are placed on a wafer

From Intel
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• Gates have features
• Speed, Cost, Power, Size,
• Transistors, resistors,.. have features (device
  characteristics)
• Speed, cost, power, size,..
• Device characteristics are determined by
• The substance used for chips
• Silicon, Silicon Germanium, Gallium Arsenide
• The transistor type
• Unipolar, bipolar
• Electronic (transistor) circuits that form the
  gates
• CMOS, BiCMOS, TTL, ECL,

Technologies
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• In order to study gate features
• Speed, Cost, Power, Size,
• We need to study substances, transistor types and
  transistor circuits
• The technology chosen
• CMOS, BiCMOS, TTL, ECL
• They have their own subfamilies
• ? CMOS HC, HCT, AC, ACT, FCT,
• ? TTL H, L, S, LS, AS,

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• Substances
• Todays chips use semiconductor substances
• Silicon is the most common semiconductor
  substance
• Silicon is the slowest substance

Transistors were implemented by germanium, a
semiconductor
Transistors are now implemented by silicon,
another semiconductor
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• Transistors
• Unipolar transistors are slower, but consume less
  power

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• Transistors Circuits
• CMOS circuits are slower, but consume less power

TTL chips are the most widely available
GPU chips are CMOS
DRAM chips are CMOS
FPGA chips are CMOS
More on gate features next week !
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• Silicon Technology Today

a)
Will there be an end to shrinking the silicon
transistor size ?
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• Fan-in
• The maximum number of inputs a gate can have
• This is purely electrical
• Determined by the technology
• The electronic circuitry determines how many
  inputs to have for reliable operation

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• Fan-out
• The number of gate inputs that can be connected
  to a gate output
• This is purely electrical
• Determined by the technology
• CMOS gates have the best fan-out
• If the fan-out is exceeded
• The output value may be noisy
• The output value may not be electrically strong
  to be interpreted as 1 or 0
• The output can be physically damaged

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• Fan-out
• In order to increase the fan-out buffers are used
• Regular buffers (not input nor output buffers)
  are used to increase the fan-out
• A buffer is an electronic circuit that has no
  logic function !
• It transfers the input to the output with a delay
  !
• It also strengthens the electrical signal
• Some buffers are also labeled as drivers since
  they can electrically drive large currents,
  hence drive many inputs
• Some buffers are designed so that they can filter
  noise on the inputs

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• Fan-out
• Increasing the fan-out

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• Technology of components/chips
• Complementary Metal Oxide Semiconductor (CMOS)
• Uses unipolar transistors
• Slower than Bipolar transistors
• Consume less power than Bipolar transistors
• Not straightforward to connect to TTL chips

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• Complementary Metal Oxide Semiconductor (CMOS)
• Low density commercial CMOS families, each with a
  different combination of speed, power, cost
• 4000 (Oldest)
• 74HC (High speed CMOS)
• 74HCT (High speed CMOS, TTL Compatible)
• 74AC (Advanced CMOS)
• 74ACT (Advanced CMOS, TTL Compatible)
• 74FCT (Fast CMOS, TTL Compatible)
• 74FCT-T (Fast CMOS, TTL Compatible with TTL VOH)
• Most high-density chips
• Microprocessors, GPUs, FPGAs, DRAMs,
  Flash-EPROMs,..

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• Complementary Metal Oxide Semiconductor (CMOS)
• CMOS chips consume very little power
• Better Fan-out than TTL chips
• CMOS chips are sensitive to static electricity
• One should not touch them
• Unless properly grounded
• A wire strapped around the wrist is connected to
  the ground
• The ground has 0v

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• Complementary Metal Oxide Semiconductor (CMOS)
• Unused gate input
• Do not leave it unconnected (floating)
• Xilinx does not allow this option !
• A No Driver warning is given by the Project
  Manager

?
y
y
b
b
The gate will not work properly
Hi-Z value observed at the input
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• Digital Engineering Terminology

U1
U2
a
Must be corrected
b
U4 input has no driver U4 input is not connected
to an output. Its input value is Hi-Z
(High-Impedance) as there is infinite impedance
(resistance) into the U4 input so no current can
flow in
a
c
U3
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• Complementary Metal Oxide Semiconductor (CMOS)
• Unused gate input
• It can be tied to a used input
• The fan-out of the b signal may be exceeded !

An available 3-input AND gate used to implement a
2-input AND gate
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• Complementary Metal Oxide Semiconductor (CMOS)
• Unused gate input
• It can be connected to 1 or 0 depending on the
  gate type, via a pull-up resistor or pull-down
  resistor

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• Complementary Metal Oxide Semiconductor (CMOS)
• Gate output
• Regular

Do not short circuit regular gate outputs
y
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• Digital Engineering Terminology

U1
U2
a
b
a
c
Must be corrected
U3
Multiple drivers on output y U3 and U4 outputs
are short circuited
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• Complementary Metal Oxide Semiconductor (CMOS)
• Gate output
• Tri-state outputs
• The output has three values !
• 1, 0 and Hi-Z High-impedance Floating
  Static voltage
• There is an extra control input, Enable, to
  enable/disable output
• ? If disabled, the output value is Hi-Z
  (high-impedance)

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• Complementary Metal Oxide Semiconductor (CMOS)
• Gate output
• Tri-state outputs
• A tri-state gate can be envisioned as a regular
  gate with a switch at the output

Output y has three values
Enable
Switch closed
Switch open
0
1
Hi-Z
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• Complementary Metal Oxide Semiconductor (CMOS)
• Gate output
• Tri-state gate outputs can be short circuited if
  only one gate is enabled at a time

Tri-state outputs are often used to implement
buses
y
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• Complementary Metal Oxide Semiconductor (CMOS)
• Gate output
• Open-drain
• An external pull-up resistor is needed

• Open-drain outputs are often used
• To drive displays and lights
• To implement buses

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• Complementary Metal Oxide Semiconductor (CMOS)
• Gate output
• Open-drain
• Gate outputs can be short circuited

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• Technology of components/chips
• Transistor-Transistor Logic (TTL)
• Uses bipolar transistors
• Consists of two sets of families
• Commercial 74xxxx
• Cheaper
• Widely available
• Military 54xxxx
• Manufactured for more stringent applications
• Expensive

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• Transistor-Transistor Logic (TTL)
• Low density commercial TTL families, each with a
  different combination of speed, power, cost,..
• 74 (Standard)
• 74L (Low-power)
• 74S (Schottky)
• 74LS (Low-power Schottky)
• 74H (High speed)
• 74AS (Advanced Schottky)
• 74ALS (Advanced Low-power Schottky)
• 74F (Fast)

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• Transistor-Transistor Logic (TTL)
• Unused gate input
• It can be left unconnected (floating)
• It can be confusing
• If the designer leaves the company and a new
  engineer works on the circuit it can be confusing
  especially if the documentation is not good !

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• Transistor-Transistor Logic (TTL)
• Unused gate input
• It can be tied to a used input
• The fan-out of the b signal can be exceeded

An available 3-input AND gate used to implement a
2-input AND gate
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• Transistor-Transistor Logic (TTL)
• Unused gate input
• It can be connected to 1 or 0 depending on the
  gate type, via a pull-up resistor or pull-down
  resistor

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• Transistor-Transistor Logic (TTL)
• Gate outputs
• Totem-pole outputs

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• Transistor-Transistor Logic (TTL)
• Gate outputs
• Tri-state outputs
• The output has three values !
• 1, 0 and Hi-Z High-impedance Floating
  Static voltage
• There is an extra control input, Enable, to
  enable/disable output
• ? If disabled, the output value is Hi-Z
  (high-impedance)

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• Transistor-Transistor Logic (TTL)
• Gate outputs
• Tri-state outputs
• A tri-state gate can be envisioned as a
  totem-pole gate with a switch at the output

Output y has three values
Enable
Switch closed
Switch open
Totem-pole gate
0
1
Hi-Z
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• Transistor-Transistor Logic (TTL)
• Gate output
• Tri-state outputs
• Outputs can be short circuited if only one gate
  is enabled at a time

Enable1
You can short circuit tri-state gate outputs
Tri-state outputs are often used to implement
buses
Enable2
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• Transistor-Transistor Logic (TTL)
• Gate output
• Open-collector
• An external pull-up resistor is needed

• Open-collector outputs are often used
• To drive displays and lights
• To implement buses

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• Transistor-Transistor Logic (TTL)
• Gate output
• Open-collector
• Gate outputs can be short circuited

Open-collector outputs can be short circuited to
implement buses
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• Analysis of the Term Project
• The term project black-box view
• The term project operation diagram
• The term project black box partitioning

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• The Analysis of the Term Project
• Polytechnic Playing Machine, Ppm
• The term project is human vs. machine
• There are two other Ppm versions which are not
  term projects
• Machine vs. machine
• Human vs. human

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• The Term Project, Ppm
• The black-box view
• Ppm is sequential (not combinational)
• A large number of FFs are used !
• We need to partition the Ppm based on major
  operations
• We have to obtain the operation diagram

60

• The Term Project, Ppm
• The black-box view
• From page 3 of the Term Project Handout

61

• The term project, Ppm
• The input/output devices of the Ppm (without
  clock)
• From page 2 of the Term Project Handout

Please be gentle with push buttons and switches
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• Ppm Simplified Operation Diagram

Reset mode
Convert the simplified operation diagram to a
(detailed) operation diagram
Press BTN3 4 times
Press BTN3 after playing RD with an adjacency
Player 1 mode
Convert each circle to one or more circles (steps
or states)
Press BTN2 to skip Press BTN2 after playing RD
without an adjacency
Press BTN2 after playing RD with an adjacency
Player 2 mode
Press BTN3 after playing RD without an adjacency
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LD0-LD2 on the FPGA board show the current state
Ppm Input/output relationship
From page 8 of the Term Project Handout
Ppm operation diagram
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Input/Output Block is active in every state
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• The Ppm Term Project Partitioning
• We have observed the following major operations
• Interfacing to the input/output devices
• Handling human players play
• Controlling display operations based on game
  rules
• Calculating new player points
• Determining the machine player play
• Hint for general partitioning
• If you cannot figure out major operations,
  partition one major operation at a time

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• The Ppm Term Project Partitioning
• Any other major operation ?
• Control (time) the operations
• All other operations

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• Digital Systems
• A digital system consists of digital circuits
• A digital system performs microoperations
• A microprocessor is a digital system
• An iPhone is a digital system
• A computer is a collection of digital systems

Intel Tukwila die
68

• The Ppm Term Project
• Ppm is a digital system !
• The Ppm term project partitioning
• First partitioning of the digital system
• Control Unit
• Data Unit
• Second partitioning (Data Unit partitioning)
• Interfacing to the input/output devices
• Handling human players play
• Controlling display operations based on game
  rules
• Calculating new player points
• Determining the machine player play

core
core
core
core
core
non-core
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• The Ppm Digital System Partitioning

From page 9 of the Term Project Handout
70

• The term project black box partitioning
• Six schematics for six blocks
• Block 1 Control Unit
• Block 2 Input/Output
• Experiment 1 is on a circuit in this block
• Block 3 Human Play
• Block 4 Play Check
• Block 5 Points Calculation file
• Block 6 Machine
• The Machine Play Block uses all other blocks
  except the Human Play Block
• These six schematics are in the ppm.sch file

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• Human Play Block, Block 3
• Has 5 inputs and 2 outputs
• Has only combinational circuits to
• Indicates that human player has played
• P1played
• Indicates that the human player has skipped
• P1skip

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• The Ppm Data Unit
• Block 3, Human Play Block
• Very simple for this version of the term project
• Makes sure the human player does not play on two
  or more positions
• Generates P1played and P1skip signals
• It is kept there so that in the future this block
  can be used to have another machine player so
  that it becomes machine vs. machine

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• The Ppm Data Unit
• Block 3, Human Play Block

Player 1 has played
Player 1 has skipped
From page 21 of the Term Project Handout
74

• The Ppm Data Unit
• Block 3, Human Play Block

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• The Ppm Data Unit
• Block 3, Human Play Block

The buffer is used to rename the input
8-to-1 MUX
Buffer
P1played
The MUX implements a combinational circuit
P1skip
A buffer does not implement any logic operation.
It transfers the input to the output. More on it
next week
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• Assignment by next lab
• Make sure that you have completed Experiment 1
• Your experiment will be collected and graded
• The last day to submit Experiment 1 as a team is
  Friday, March 7, 2014
• We will also collect Experiment 2, by Friday,
  March 7, 2014
• It will be graded and returned by the following
  lab

Submit your Experiment 1 during a lab session
! Not during Open Lab Hours !
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• Digital Design Conventions
• Digital Circuit Drawing Conventions
• Project Information is placed in the lower right
  corner
• Company name, and address
• Project name,
• Project dates, etc.

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• Digital Design Conventions
• Digital Circuit Drawing Conventions
• CS2204 Related
• Part 1 of Term Project Design Checks
• The team info on the lower right corner is
• ? In the Name area enter the name of the
  student who designed
• the schematic the names of the other
  members of the team
• ? In the Title area enter CS 2204
  Your Lab Section
• Spring 2014
• ? Place some space before
  CS 2204 so that it is not
• right next to the name
  of the block

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• Digital Design Conventions
• Digital Circuit Drawing Conventions
• Part 2 of Term Project Design Checks
• Remember to beautify the circuit before
  submitting it
• Place components of a (sub)block next to each
  other and separate (sub)blocks from each other
• Components form horizontal and vertical lines
• Only horizontal and vertical wires drawn
• No need to draw long wires
• ? One can draw short wires and name them
• No unnecessary wire turns
• No Unnecessary line tanglings
• Wires are not drawn over components, buffers, pads

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• Digital Design Conventions
• Logic Circuit Design Conventions
• Part 3 of Term Project Design Checks
• If a component has multiple outputs, make sure
  you use the needed ones
• If an output is not needed, leave it unconnected
• Outputs should not be short-circuited unless they
  are tri-state
• But, we will not use tri-state outputs this
  semester !

81

• Digital Design Conventions
• Logic Circuit Design Conventions
• Part 4 of Term Project Design Checks
• Make sure the experiment folder name is correct
• Last experiment folder is used for the current
  experiment ?
• The termproject folder is used as the experiment
  folder ?
• More than 6 schematics are used ?

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• Digital Design Conventions
• Logic Circuit Design Conventions
• Part 5 of Term Project Design Checks
• Do not forget to save schematics
• Then, do a Xilinx IMPLEMENTATION to have the
  changes affect the output
• Read the warnings and errors listed
• Confirm that the warnings are acceptable
• The FPGA chip utilization does not have to be 6
• ? The utilization depends on the
  strategy, the intelligence of
• the machine player designed
• Perform simulations
• If an output value is Hi-Z during simulation,
  make sure it is correct

83

• Digital Design Conventions
• Digital Circuit Printing Conventions
• The printout must be readable
• Labels, component names, symbols, etc.
• If the circuit is large, it must be printed on
  several pages
• The sheets must be attached to each other
• Lines, labels, etc. must be continuous from one
  sheet to the next

84

• Common Logic Errors
• Discovering logic errors by means of simulations

The correct expression
Must be corrected
Input a is input b by mistake !
U3
Must be corrected
The OR gate is an AND gate by mistake !
85

• Common Logic Errors
• Discovering logic errors by means of simulations

U2 has no Load U2 output is not used
Must be corrected
U1
U2
a
Must be corrected
b
U4 input has no driver U4 input is not connected
to an output. Its input value is Hi-Z
(High-Impedance) as there is infinite impedance
(resistance) into the U4 input so no current can
flow in
a
c
Must be corrected
U3
Multiple drivers on output y U3 and U4 outputs
are short circuited
86

• QUESTIONS ?

Make sure you have the LABS account and see the S
drive Make sure you have installed WebPACK 12.4
on your laptop Make sure you create a CS2204
folder on both
Read slides at the end to learn about the
software, Project Manager, Schematic design and
other related topics
Do not leave the lab before your partners
finish ? Help your partners
Continue reading the Term Project handout
Think about the machine player strategy
87

• Todays Individual Xilinx Work
• We will continue with the 4-bit 2-to-1 MUX in
  Block 2. We will use our knowledge of 2-to-1
  MUXes to modify a portion of the term project to
  develop a 4-bit 2-to-1 MUX in the Human Play
  Block (Block 3)
• The 2-to-1 MUX expression is the same as the one
  obtained in class
• We will obtain its schematic (circuit diagram)
• We will design a 4-bit MUX by using 1-bit MUXes
• We will do a schematic check
• We will test our design on the computer assuming
  ideal gates
• Do logic simulations
• We will do a Xilinx IMPLEMENTATION of the project
• To create the bit file
• We will test our design on the FPGA board
• We will program the FPGA chip download the bit
  file
• We will use switches and a LED light to test our
  design on the FPGA board
• Help our partners complete todays project
• We will continue reading the Term Project handout
• Also read slides at the end to learn about the
  software, Project Manager, Schematic design and
  other related topics

88

• Todays Individual Xilinx Lab Work
• (If you did not do it last week) Copy the
  termproject folder and paste it as the exp1
  folder to experiment with the Ppm schematics
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• Open the schematics and analyze the schematics
• Make sure the team info is placed on all the
  schematics !
• Study the 4-bit 2-to-1 MUX schematic in the
  Input/Output Block in schematic 2 of the term
  project to refresh your memory on the MUX
• Replace the 4-bit MUX in Block 2 with four 1-bit
  MUXes in Block 3 of the term project by using the
  circuitry shown on pages 1 and 2 of Handout 3 and
  Xilinx components
• Do a schematic check on the new design
• Perform functional simulations on the 4-bit
  2-to-1 MUX

89

• Todays Individual Xilinx Lab Work
• Perform a Xilinx IMPLEMENTATION
• Download the Ppm project to the FPGA chip and
  play the game and to verify that the schematic
  works correctly
• Program the FPGA chip
• Test the Ppm to see if it is working
• Play the game on the FPGA board
• If it does not work, inspect your circuit in
  Block 3 and correct the circuit
• Help your partners complete todays project
• Submit your exp1 project once everyone completes
  the design
• Continue reading the Term Project handout
• Study and play the other two types of the Ppm
  game to think more about the our machine players
  strategy
• Human vs. human ppmhvsh
• Machine vs. machine ppmmvsm
• Think about the playing strategy of the machine
  player that will be designed
• Also read slides at the end to learn about the
  software, Project Manager, Schematic design and
  other related topics

90

• Todays Individual Xilinx Lab Work
• (If you did not do this step last week) Copy the
  termproject folder in the CS2204 folder on the S
  drive and paste it as the exp1 folder to
  experiment with the Ppm schematics as explained
  in the Lab 3 presentation
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• Double click on the Xilinx ISE Design Suite icon
  on your desktop

91

• Todays Individual Xilinx Work
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• Xilinx will show a Tip of the Day window in the
  foreground and the ISE Project Navigator window
  in the background

92

• Todays Individual Xilinx Work
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• The ISE opens the last project you worked on by
  default
• Though this can be changed by changing the
  Preferences settings
• If you did not open any Xilinx project, it will
  not open any project as you saw on the previous
  slide and see below
• Click on OK to close the Tip of the Day window

Note that this window can be turned off by
clicking on this
93

• Todays Individual Xilinx Work
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• After the Tip of the Day window is closed you
  will see the following

94

• Todays Individual Xilinx Work
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• Click on Open Project... on the Start panel on
  the left to start opening the term project

95

• Todays Individual Xilinx Work
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• The Open Projectwindow will pop up asking you
  to select the project folder which is termproject
• Select the project folder S\CS2204\exp1 by
  using typical Windows operations
• You will see the partial content of the exp1
  folder where all six folders and the Xilinx ISE
  Project file are shown

96

• Todays Individual Xilinx Work
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• Double click on Xilinx ISE Project

97

• Todays Individual Xilinx Work
• Start the Xilinx ISE software and open the Ppm
  project in the exp1 folder
• Xilinx will open the term project in the exp1
  folder

98

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Double click on ppm (ppm.sc) to view the six
  schematics

99

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Take a look at the six schematics for the six
  blocks of the term project
• Block 1 Control Unit
• Block 2 Input/Output
• Block 3 Human Play
• Block 4 Play Check
• Block 5 Points Calculation
• Block 6 Machine Play
• These six schematics are in the ppm.sch file

100

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Double click on ppm (ppm.sc) to view the six
  schematics
• Notice that as the schematic file is open the
  first schematic sheet is shown and also the left
  panel changes to the Options panel

First schematic sheet
First schematic sheet Control Unit
101

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Click on 2 to the left of the schematic sheet to
  view the second schematic sheet

Second schematic sheet
Second schematic sheet Input/Output Block
102

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Click on 3 to the left of the schematic sheet to
  view the third schematic sheet

Third schematic sheet
Third schematic sheet Human Play Block
103

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Click on 4 to the left of the schematic sheet to
  view the fourth schematic sheet

Fourth schematic sheet
Fourth schematic sheet Play Check Block
104

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Click on 5 to the left of the schematic sheet to
  view the fifth schematic sheet

Fifth schematic sheet
Fifth schematic sheet Points Calculation Block
105

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Click on 6 to the left of the schematic sheet to
  view the sixth schematic sheet

Sixth schematic sheet Machine Play Block
Sixth schematic sheet
106

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• There are six schematics !

We are covering these schematics in detail !
The Term Project handout discusses the schematics
in detail !
107

• Todays Individual Xilinx Work
• Open the schematics and analyze the schematics
• Take a look at the six schematics for the six
  blocks of the term project
• Blocks 1, 2, 3, 4 and 5 are core blocks
• All of their circuits are given
• Block 6 is completely non-core
• Students will replace all the circuits with their
  own circuits

108

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• Take a look at the six schematics for the six
  blocks of the term project
• Each block (schematic) consists of subblocks and
  subsubblocks
• The software identifies each schematic sheet by
  automatically assigning it a number
• Subblocks and subsubblocks are identified by
  their names and distance and lines between them
  on the schematic sheet
• Common document processor editing rules and key
  sequences apply to edit schematics

109

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• All components use the same convention that
  inputs are on one side and outputs are on the
  other side
• There are exceptions like 4-bit ADDers, and
  sequential circuits (flip-flops, registers,
  counters, etc.) that additional inputs are on the
  remaining two sides as well
• Black boxes students will implement (M2 and M3)
  use the same convention
• Inputs are one side
• Outputs are on the other side

110

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• Enter team information on the schematics if it
  is not entered
• To enter the team info schematic 1 switch to
  schematic 1 and zoom into the lower right corner
  where project information is shown

111

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• Enter team information on the schematics if it
  is not entered
• To enter the team info on schematic 1 switch to
  schematic 1 and zoom into the lower right corner
  where project information is shown
• Right click on the project information object
• Select Object Properties
• In the NameFieldText area enter the names of the
  members of the team
• In the Title area enter CS 2204 Your Lab
  Section Spring 2014
• Place some space before CS 2204 so that it is
  not right next to Ppm Control Unit

112

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• Enter team information on the schematics if it
  is not entered
• To enter the team info on schematic 1 switch to
  schematic 1 and zoom into the lower right corner
  where project information is shown
• Save the schematic to record the changes
• After you save, the Date area is automatically
  entered the date and time the save was done
• After you enter all the information, the project
  information area in schematic 1 will look like as
  follows for an imaginary team

113

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• Enter team information on the schematics if it is
  not entered
• The Project Navigator window after the schematic
  is saved is different where there are
  symbols next to Synthesis, Implement Design and
  Generate Programming File steps in the Processes
  section, signaling that they must be done to
  incorporate these changes to the design

114

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• Enter team information on the schematics if it is
  not entered
• Repeat these steps above for the remaining five
  schematics so that they all have the same team
  information
• The Project Navigator window will still have
  symbols next to Synthesis, Implement Design and
  Generate Programming File steps in the Processes
  section

115

• Todays Individual Xilinx Lab Work
• Open the schematics and analyze the schematics
• Enter team information on the schematics if it is
  not entered
• Repeat these steps above for the remaining five
  schematics so that they all have the same team
  information
• The Project Navigator window will still have
  symbols next to Synthesis, Implement Design and
  Generate Programming File steps in the Processes
  section
• In order to record these changes, we have to save
  the schematic and do a synthesis
• Save the schematic
• Perform a Synthesis operation by double clicking
  on the Synthesize XST process on the Project
  Navigator panel
• Switch to the Design Summary panel and notice
  that there are 137 warnings
• ? We know this due to the fact that we
  are working on a copied and
• pasted project and the ISE is
  complaining about the paths
• Right click and select ReRun on the Synthesize
  XST process on the Project Navigator panel to
  eliminate the unnecessary warnings
• ? The new number of warnings is 63 as it
  is the case with the term
• project and the symbol next to the
  Synthesize XST process is

116

• Todays Individual Xilinx Lab Work
• Study the 4-bit 2-to-1 MUX schematic in the
  Input/Output Block in schematic 2 of the term
  project to refresh your memory on the MUX
• Take a look at the MUX labeled U80
• DDISP circuit is a 4-bit 2-to-1 MUX
• Selects between DISP and P2PT
• Uses DISPSEL0 as the select signal

DDISP operation table
Operation
DISPSEL0
0 DDSIP DISP
1 DDISP P2PT
We need a 4-bit 2-to-1 MUX
Do we design it ?
117

• Todays Individual Xilinx Lab Work
• Study the 4-bit 2-to-1 MUX schematic in the
  Input/Output Block in schematic 2 (ppm2.sch) of
  the term project to refresh your memory on the
  MUX
• Take a look at the MUX labeled U80
• DDISP circuit is a 4-bit 2-to-1 MUX

We need a 4-bit 2-to-1 MUX
We do not design it It has already implemented
it is satisfactory for us
u74_157 A 4-bit 2-to-1 MUX
118

• Todays Individual Xilinx Lab Work
• Study the 4-bit 2-to-1 MUX schematic in the
  Input/Output Block in schematic 2 of the term
  project to refresh your memory on the MUX
• Take a look at the MUX labeled U80
• What is the G input ?
• The G input is a control input which is the
  enable input
• If the Enable input is 1 all four outputs are 0
• The G input is active low !
• The circle (bubble) at the G input indicates it
  is active low ! simulations on the 4-bit 2-to-1
  MUX in to refresh your memory on the MUX and
  simulations

The 4-bit 2-to-1 MUX operation table
S
Operation
G
1 X Y 0
0 0 Y A
0 1 Y B
119

• Todays Individual Xilinx Lab Work
• Study the 4-bit 2-to-1 MUX schematic in the
  Input/Output Block in schematic 2 of the term
  project to refresh your memory on the MUX
• Take a look at the MUX labeled U80
• What is the GND ?
• GND Ground 0 Volts 0
• The G input is permanently connected to 0 !
• Since the Enable is permanently 0, the outputs
  are always enabled

How DDISP uses the MUX
Operation
DISPSEL0
G
1 X DDISP 0
0 0 DDISP DISP
0 1 DDISP P2PT
G 0 ? Only these two rows are valid for U80
120

• Todays Individual Xilinx Lab Work
• Study the 4-bit 2-to-1 MUX schematic in the
  Input/Output Block in schematic 2 of the term
  project to refresh your memory on the MUX
• Take a look at the MUX labeled U80
• Implementing a 4-bit 2-to-1 MUX ?
• Based on major operations on the operation table
  !
• Major operations are not explicit on the previous
  operation table
• Obtain a more detailed operation table
• There are four identical major operations 1-bit
  2-to-1 MUXing