Logic Families and Their Characteristics

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Chapter 9

• Logic Families and Their Characteristics

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Objectives

• You should be able to
• Analyze internal circuitry of a TTL NAND gate for
  both HIGH and LOW output states.
• Determine IC input and output voltage and current
  ratings from the manufacturers data manual.
• Explain gate loading, fan-out, noise margin, and
  time parameters.

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Objectives

• (Continued)
• Design wired-output circuits using open-collector
  TTL gates.
• Discuss the differences and proper use of the
  various subfamilies within both TTL and CMOS ICs.
• Describe the reasoning and various techniques for
  interfacing between the TTL, CMOS, and ECL
  families of ICs.

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The TTL Family

• Bipolar transistors
• Physical model
• Symbol
• Diode equivalent

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The TTL Family

• Two-input NAND gate
• Multi-emitter transistor
• Totem-pole output stage
• HIGH level output typically 3.4 V
• LOW level output typically 0.3 V

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The TTL Family

• 7400 two-input NAND gate

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TTL Voltage and Current Ratings

• Input/output current and fan-out
• Source current IOH
• Sink current IOL
• Low-level input current IIL
• High level input current IIH

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TTL Voltage and Current Ratings

• Example of TTL gate sinking input currents from
  two gate inputs using logic symbols

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TTL Voltage and Current Ratings

• Example of TTL gate sinking input currents from
  two gate inputs using schematic symbols

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TTL Voltage and Current Ratings

• Example of TTL gate sourcing current to two gate
  inputs using logic symbols

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TTL Voltage and Current Ratings

• Example of TTL gate sourcing current to two gate
  inputs using schematic symbols

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TTL Voltage and Current Ratings

• Summary of I/O current and fan-out
• Low-level input current IIL 1.6 mA (-1600 µA)
• High level input current IIH 40 µA
• (The minus sign indicates current leaving the
  gate)
• IOL low-level output current 16 mA (16,000
  µA)
• IOH high-level output current -400 µA (-800
  µA for some)
• (Max capability of a gate to sink or source
  current)
• Fan-out is max number of gate inputs that can be
  connected to a standard ttl gate output.
• Typically fan-out 10.

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TTL Voltage and Current Ratings

• Input/Output Voltages and Noise Margin
• Noise margin The difference between high level
  voltages and low level voltages

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TTL Voltage and Current Ratings

• Input/Output Voltages and Noise Margin (graphical
  representation)

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Discussion Point

• Locate the voltage and current ratings covered so
  far on the typical data sheet given in Figure 9-8.

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Other TTL Considerations

• Pulse-Time Parameters
• Rise Time Measured from 10 level to 90 level

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Other TTL Considerations

• Pulse-Time Parameters
• Fall Time Measured from 90 level to 10 level

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Other TTL Considerations

• Pulse-Time Parameters
• Propagation Delay (tPLH and tPHL)

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Other TTL Considerations

• Power dissipation
• Total power supplied to the IC power terminals
• Open-collector outputs
• Upper transistor removed from totem-pole
• Can sink current
• Can not source current
• Pull-up resistor used

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Other TTL Considerations

• Wired-output operation
• Outputs from two or more gates tied together
• Wired-AND logic

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Figure 916 Wired-ANDing of open-collector
gates for Example 94 (a) original circuit and
(b) alternative gate representations used for
clarity.
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Figure 913 (continued) TTL NAND with an
open-collector output (a) circuitry (b) truth
table.
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Figure 913 TTL NAND with an open-collector
output (a) circuitry (b) truth table.
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Figure 914 Using a pull-up resistor with an
open-collector output. (a) Adding a pull-up
resistor to a NAND gate. (b) When Q4 inside the
NAND is on, Vout 0 V. (c) When Q4 is off, the
pull-up resistor provides 5 V to Vout.
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Other TTL Considerations

• Disposition of unused inputs and unused gates
• Open inputs degrade noise immunity
• On AND and NAND tied HIGH
• On OR and NOR tied LOW
• Unused gates force outputs HIGH

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Other TTL Considerations

• Power supply decoupling
• Connecing 0.01 to 0.1 ?F capacitor between VCC
  and ground pins
• Reduces EMI radiation
• Reduces effect of voltage spikes from power supply

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Improved TTL Series

• 74HXX series
• Half the propagation delay
• Double the power consumption
• Schottky TTL
• Low-power (LS)
• Advanced low-power (ALS)
• 74FXX
• Reduced propagation delay

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Figure 917 Schottky-clamped transistor (a)
Schottky diode reduces stored charges and (b)
symbol.
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The CMOS Family

• MOSFETs
• Metal oxide semiconductor field-effect
  transistors
• PMOS and NMOS type substrates

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The CMOS Family

• MOSFETs
• Higher packing densities than TTL
• Millions of memory cells per chip
• See Table 9-2 in your text

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Table 92 Basic MOSFET switching
characteristics.
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Figure 919 CMOS inverter formed from
complementary N-channel/P-channel transistors.
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The CMOS Family

• Handling CMOS devices
• Avoid electrostatic discharge
• CMOS availability
• 4000 series - original CMOS line
• 40H00 series - faster
• 74C00 series - pin compatible with TTL
• 74HC00 and 74HCT00 series
• Speedy, less power, pin compatible, greater noise
  immunity and temperature operating range

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Figure 921 Wearing a commercially available
wrist strap dissipates static charges from the
technicians body to a ground connection while
handling CMOS ICs.
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The CMOS Family

• CMOS availability
• 74- biCMOS series - low power and high speed
• 74-low voltage series
• See appendix B
• Nominal supply voltage of 3.3 V
• 74AHC and 74AHCT series
• Superior speed
• Low power consumption
• High output drive current

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The CMOS Family

• 74AVC advanced very-low-voltage CMOS logic
• Faster speed
• Very low operating voltages
• 3.3 V, 2.5 V, 1.8 V, 1.5 V and 1.2 V

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Emitter-Coupled Logic

• Extremely fast
• Increased power dissipation
• Uses differential amplifiers

Figure 9-22
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Emitter-Coupled Logic

• Newer technologies
• Integrated injection logic (I2L)
• Silicon-on-sapphire (SOS)
• Gallium arsenide (GaAs)
• Josephson junction circuits

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Comparing Logic Families

• Performance specifications

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Comparing Logic Families

• Propagation delay versus power

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Comparing Logic Families

• Power supply current versus frequency

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Interfacing Logic Families

• TTL to CMOS

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Interfacing Logic Families

• TTL to CMOS
• Pull-up resistor

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Interfacing Logic Families

• CMOS to TTL

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Interfacing Logic Families

• CMOS to TTL

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Interfacing Logic Families

• Worse-case values
• See Table 9-4 in your text.

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Interfacing Logic Families

• Level Shifting
• Level-shifter ICs 4049B and 4050B

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Interfacing Logic Families

• Level Shifting
• Level-shifter ICs 4504B

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Interfacing Logic Families

• ECL Interfacing

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Summary

• There are basically three stages of internal
  circuitry in a TTL (transistor-transistor-logic)
  IC input, control, and output.
• The input current (IIL or IIH) to an IC gate is a
  constant value specified by the IC manufacturer.

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Summary

• The output current of an IC gate depends on the
  size of the load connected to it. Its value
  cannot exceed the maximum rating of the chip, IOL
  or IOH.
• The HIGH- and LOW-level output voltages of the
  standard TTL family are not 5 V and 0 V but
  typically are 3.4 V and 0.2 V.

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Summary

• The propagation delay is the length of time that
  it takes for the output of a gate to respond to a
  stimulus at its input.
• The rise and fall times of a pulse describe how
  long it takes for the voltage to travel between
  its 10 and 90 levels.

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Summary

• Open-collector outputs are required whenever
  logic outputs are connected to a common point.
• Several improved TTL families are available and
  continue to be introduced each year providing
  decreased power consumption and decreased
  propagation delay.

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Summary

• The CMOS family uses complementary metal oxide
  semiconductor transistors instead of the bipolar
  transistors used in TTL ICs. Traditionally, the
  CMOS family consumed less power but was slower
  than TTL. However, recent advances in both
  technologies have narrowed the differences.

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Summary

• The BiCMOS family combines the best
  characteristics of bipolar technology and CMOS
  technology to provide logic functions that are
  optimized for the high-speed, low-power
  characteristics required in microprocessor
  systems.

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Summary

• A figure of merit of IC families is the product
  of their propagation delay and power consumption,
  called the speed-power product (the lower, the
  better).
• Emitter-coupled logic (ECL) provides the
  highest-speed ICs. Its drawback is its very high
  power consumption.

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Summary

• When interfacing logic families, several
  considerations must be made. The output voltage
  level of one family must be high and low enough
  to meet the input requirements of the receiving
  family. Also, the output current capability of
  the driving gate must be high enough for the
  input draw of the receiving gate or gates.

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