FYP PROJECT PRESENTATON

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FYP PROJECT PRESENTATON

• Alan Concannon
• 4ECE
• Supervisor Dr Fearghal Morghan
• Co-SupervisorJohn Maher

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Presentation Overview

• Project Description/Specification
• Current Progress
• Future Work

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Project Specification(Original)

• Perform further development on an existing
  Digilent Spartan-3 FPGA based application
• Perform a range of DSP, image and data processing
  functions.

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Project Specification(Updated)

• Export an existing Spartan 3 FPGA based
  application onto the Digilent Nexys Board
• Implement extra DSP functionality
• e.g. An FIR Filter

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System Overview
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Existing Hardware
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New Hardware - Nexys
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Graphical User Interface
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Current Work/Progress

• appliedVHDL course completed
• Reviewed Shane Agnews FYP
• Reviewed Antoin OhAllmhurains FYP
• Downloaded counter program to Nexys board to
  prove functionality
• Nexys Board ready for CSR access
• Started implementing Nexys memory module in VHDL

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Future Work

• Implement new RAM BFM and Memory controller
• Implement current project with Nexys board
  Completely functional
• Design an FIR filter in VHDL and Implement in the
  Project

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Questions?