MAPS

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Discussion of process features to target optimum
monolithic SOI Pixel Detectors
Grzegorz DEPTUCH Fermi National Accelerator
Laboratory, Batavia, IL, USA

• OUTLINE1) objectives of optimization,
• 2) conclusions from previous work,
• 3) Design details of pixel imaging detector
  MAMBO,
• 4) Achievements, observations and
  investigations, 5) Conclusions on current status
  of the technology,
• 6) Discussion around necessary changes to the
  process,
• 7) Conclusions.

email deptuch_at_ieee.org
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Objectives
Fabrication of detecting layer and electronics
in the same fabrication flow requires
investigating potential improvements from
different angles
Optimization of detector grade handle wafer for
carrier lifetime and charge transport properties
Optimization of the SOI electronics for designs
of readout circuits with dominant presence of
analog functions
Cohesion of the detector layer and the
electronics, minimisation of mutual detrimental
coupling
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Summary and conclusions from pre-SOPIX works

• work related to detection of ionizing radiation

F. Pengg, Monolithic Silicon Pixel Detectors in
SOI Technology, CERN/ECP, RD19 collaboration,
January 1996, Ph.D. thesis
Coupling issue recognized!!!
J. Marczewski, et al., Technology development
for SOI monolithic detectors, Nucl. Instr. and
Meth. A, 560, 2006, 26-30
Nested buried wells proposed!!!
GOOD in CONCEPTS but NOT SUCCESSFUL BECAUSE
OF LACK OF SUFFICIENTLY ADVANCED TECHNOLOGY

• Need for careful shileding between the SOI
  electronics and the detector underneath the BOX
  ()
• Thick SOI (quasi-bulk process for optimum analog
  performance)

Thick SOI layer
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Summary and conclusions from pre-SOPIX works

• work related to visible light imaging

W.Zhang M.Chan H.Wang Ko, P.K., Building
hybrid active pixels for CMOS imager on SOI
substrate, SOI Conference, 1999. Proceedings.
1999 IEEE International,1999 , 102 - 103
Path of evolution
No attention to coupling
X.Zheng, C.Wrigley, G.Yang, B.Pain, High
responsivity CMOS imager pixel implemented in SOI
technology, SOI Conference, 2000 IEEE
International 2000, 138 - 139
Excluded from sensitivity
B.Pain, Ch.Sun, X.Zheng, S.Seshadri, T.J.
Cunningham, SOI-based Monolithic Imaging
Technology for Scientific Applications, 2007
international image sensors workshop, June 6-10,
2007 Ogunquit, ME
Pinning layer implanted!!!
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Implementation of buried P-well in current OKI
process
n- -type

• BPW is helpful in maintaining constant potential
  under any circuitry that is placed at the
  periphery of the matrix of pixels.
• The potential control underneath the BOX may be
  achieved by designing a closely spaced matrix of
  PSUB contacts. It was shown that this works
  relatively well on the fabricated circuits (the
  cost is a penalty of some are lost for multiple
  PSUB contacts).
• BPW is not providing any benefit for protection
  against charging of the BOX layer as a result of
  accumulation ionizing doses of the incident
  radiation. The circuitry is exposed directly to
  the modulation of conduction resulted from the
  charged oxide of the BOX.

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Review of role of BPW layer
Generally electric field in the p-on-n detector
is not uniform in case of very small p-type
implant separated by large lateral
distance Potential pockets can be created with no
electric field thus no charge collectio from
some regions
The distribution of electric field can be
improved by increasing effective sizes of
implants using BPW islands Smaller distances
between BPW islands may lead to shorts,
especially if some residual p-type effective
doping occurs underneath the BOX
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Review of role of BPW layer
Extension of effective size of diodes achieved by
adding BPW over PSUB is not bringing any good
inside pixels, direct coupling paths sending all
transient interferences to the input of an
in-pixel amplifier, additionally multiple
feedback path are created taht may lead to
instability of the processing chain
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Review of role of BPW layer
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Review of role of BPW layer
This is not BPW, but contamination that may
change effective conduction type to p type
directly underneath BOX
The distribution of electric field can be
improved by increasing effective sizes of
implants using BPW islands Smaller distances
between BPW islands may lead to shorts,
especially if some residual p-type effective
doping occurs underneath the BOX
Generally electric field in the p-on-n detector
is not uniform in case of very small p-type
implant separated by large lateral
distance Potential pockets can be created with no
electric field thus no charge collectio from
some regions
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Design details of pixel imaging detector MAMBO
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Achievements, observations and investigations
MAMBO I single pixel test

• PMOS biased at VGSconst as a feedback resistor
  (50 MW)

• shaper design in MAMBO II used longer L
  half-H-Gate design for feedback transitor (SBC)

Transistor with floating body was used (poor
precision SPICE models gave wrong value of gds)
later measurements showed very small equiv.
resistance
As a result, required values of feedback resistor
were obtained. Empirical approach is needed to
compensate for insufficient device modeling
0.20 mm
0.15 mm
MAMBO II
MAMBO I
W/L0.63u/0.3u
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Achievements, observations and investigations
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Achievements, observations and investigations
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Achievements, observations and investigations
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Achievements, observations and investigations
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Achievements, observations and investigations
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Achievements, observations and investigations
MAMBO II single pixel test
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Achievements, observations and investigations
M. Connell, et all. Impact of Mobile Charge on
Matching Sensitivity in SOI Analog Circuits, 2007
IEEE/SEMI Advanced Semiconductor Manufacturing
Conference
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Achievements, observations and investigations
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Achievements, observations and investigations
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Achievements, observations and investigations
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Achievements, observations and investigations
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Conclusions on current status of the technology
M. Connell, et all. Impact of Mobile Charge on
Matching Sensitivity in SOI Analog Circuits, 2007
IEEE/SEMI Advanced Semiconductor Manufacturing
Conference
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Discussion around necessary changes to the process

• minimum

• tBOX200nm, tGOX4.5nm, wide oxide areas favors
  positive charge trapping, threshold voltage
  shifts, ions flows and transistors shows poor
  behavior

CURRENT VIEW
Isolation of vertical contacts achieved naturaly
as contact openings are etched in oxide

• all is the same but bottom gate action is
  dcreased proportionally to tBOX

INCREASE THICKNESS OF BOX
increase of tBOX may affect metrology on the
production line
It is not believed that only only increase of
tBOX will be enough
this is only partial improvement!
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Discussion around necessary changes to the process

• real improvement (suggestion for minimum process
  complication) shift from FD-SoI to
  quasi-bulk-SoI this is necessary!!!

I step Grow epitaxial silicon on UNIBOND wafers
from SOITEC
The grown layer will be used for the substrate
for transistors, no isolation of transistor
islands!! to achieve screening
II step blanket implantation of p-type film and
n-type film island
Important is that p-type film is left around
cuts, it is fully enclosed by n-film for self
centering
III step cuts of contact holes, S/D implants,
cuts of STI
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Discussion around necessary changes to the process

• real improvment (prepared in such way that
  minimum modificatio)

- It is wise to stay with n-type detector silicon

- Transistors will be closer to bulk devices
(advantage is that the continuous film will be
AC-grounded, but each n and p type island will be
fully isolated
Islands hosting pmos transistors will be
AC-grounded
IV step fill with oxide and planarization
P-type film areas left around opening will be
left floating. After etching opening for S/D,
poly-gate and diode openings there will not be
needed to passivate walls with exposed p-type
Silicon with oxide
After this step all processing is the same as it
was for the original OKI-SOI process!
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Discussion around necessary changes to the process
V step etch contact opening and fill
Eacthing of contact opening is self centered, the
fill material will be in contact wit p-type
material but the opposite side of the diode will
be grounded
- The contact between the fill metal and the
floating p-type material will result in some
extra capacitance, however it should not be
meanigful for amplifiers based on the virtual
ground principle as it is the optimum
implementation for the readout circuitry!
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Conclusions

• The SOIPIX collaboration formed around KEK is a
  opportunity to explore new 0.15 mm 1P/5M and 0.20
  mm 1P/4M FDSoI CMOS processes by OKI altered to
  allow charge collection from H-R substrate,
• Within two available runs, we managed to obtain
  working design of the continuous time pixel
  circuit,
• We have problems with counters switchable to
  shift registers for outputing the data problem
  is understood and could be avoided if parasitics
  extraction was available,
• Effort spent on extensive tests led to
  conclusion on unavoidable deeper adaptations of
  the process to make it suitable for monolithic
  detectors,

• Guidance for the optimum process has been drawn
  can it be introduced by the foundry?
• Our experience with 3D-IC using 0.18 mm FDSoI
  process by MIT-LL and discussions with experts
  suggests excluding the use of FD-SoI for designs
  with analog,
• more runs and more efficient communication are
  needed to forge the design dominant part of
  learning occurs through experimenting (modeling
  required),