FINITE STATE MACHINES - II

1
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• PARTITIONING MINIMIZATION PROCEDURE
• VENDING MACHINE EXAMPLE
• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
• PROCEDURE
• EXAMPLE
• ALGORITHMIC STATE MACHINES (ASM) CHARTS
• COMPLETE FSM DESIGN EXAMPLE
• PARALLEL-TO-SERIAL CONVERTER WITH PARITY GENERATOR

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
2
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• PARTITIONING MINIMIZATION PROCEDURE
• DEFINITION Two states Si and Sj are said to be
  equivalent if and only if for every input
  sequence , the same output sequence will be
  produced regardless of whether Si or Sj are the
  initial states.
• DEFINITION OF 1-SUCCESSOR If the machine moves
  from state Si to state Sv when input w 1, then
  we say that Sv is a 1-successor of Si
• DEFINITION OF 0-SUCCESSOR If the machine moves
  from state Sj to state Su when input w 0, then
  we say that Su is a 0-successor of Si
• IF STATES Si AND Sj ARE EQUIVALENT, THEN THEIR
• CORRESPONDING K-SUCCESSORS (FOR ALL K) ARE ALSO
• EQUIVALENT.

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
3
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
• DEFINITION A PARTITION CONSISTS OF ONE OR MORE
  BLOCKS, WHERE EACH BLOCK COMPRISES A SUBSET OF
  STATES THAT MAY BE EQUIVALENT, BUT THE STATES IN
  A GIVEN BLOCK ARE DEFINITELY NOT EQUVALENT TO THE
  STATES IN THE OTHER BLOCK.

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
4
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
• PROCEDURE
• 1) ALL STATES BELONG TO THE INITIAL PARTITION P1
  
• 2) P1 IS PARTITIONED IN BLOCKS SUCH THAT THE
  STATES IN EACH BLOCK GENERATE THE SAME
  OUTPUT.
• 3) CONTINUE TO PERFORM NEW PARTITIONS BY TESTING
  WHETHER THE K-SUCCESSORS OF THE STATES IN EACH
  BLOCK ARE CONTAINED IN ONE BLOCK. THOSE STATES
  WHOSE K-SUCCESSORS ARE IN DIFFERENT BLOCKS
  CANNOT BE IN ONE BLOCK.
• 4) PRCEDURE ENDS WHEN A NEW PARTITION IS THE SAME
  AS .THE PREVIOUS PARTITION

5
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
• EXAMPLE Consider the following state transition
  table
• P1 (ABCDEFG)
• P2 (ABD)(CEFG) Diff. Outputs.
• Because (CEFG) 0-successors are (FFEF) in
  same block,
• (CEFG) 1-successors are (ECDG)
  in diff. block,
• F must be different from C, E and G
• P3 (ABD)(CEG)(F)
• P4 (AD)(B)(CEG)(F)
• Same process for (AD) and (CEG) gives
• P5 (AD)(B)(CEG)(F)
• P5 P4

6
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
• EXAMPLE (CONTINUES) MINIMAL STATE TRAMSITION
  TABLE
• ORIGINAL TABLE
• P4
  (AD)(B)(CEG)(F)
• 
  MINIMIZED TABLE

7
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• VENDING MACHINE EXAMPLE
• Design an FSM that will dispense candy under the
  following
• conditions
• 1.- The machine accepts nickels and dimes
• 2.- 15 cents releases a candy from the machine
• 3.- If 20 cents is deposited, the machine will
  not return the change, but it credit the buyer
  with 5 cents and wait for the buyer to make a
  second purchase

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
8
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• VENDING MACHINE EXAMPLE (Continues)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
9
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• VENDING MACHINE EXAMPLE (Continues)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
10
FINITE STATE MACHINES - II

• STATE MINIMIZATION VENDING MACHINE EXAMPLE
  (Continues)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
11
FINITE STATE MACHINES - II

• STATE MINIMIZATION
• VENDING MACHINE EXAMPLE (Continues)
• P1 (S1, S2, S3,
  S4, S5, S6, S7, S8, S9)
• P2
  (S1, S2, S3, S6)(S4, S5, S7, S8, S9)
• 
  P3 (S1)(S3)(S2, S6)(S4, S5, S7, S8, S9)
• 
  P4 (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9)
• 
  P5 (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
12
FINITE STATE MACHINES - II

• STATE MINIMIZATION VENDING MACHINE EXAMPLE
  (Continues)
• MINIMIZED STATE TRANSITION TABLE AND DIAGRAM

13
FINITE STATE MACHINES - II

• STATE MINIMIZATION VENDING MACHINE
  EXAMPLE (Continues)
• MINIMIZED STATE TRANSITION DIAGRAM Moore-type
  versus Mealy-type
• MOORE-TYPE
  MEALY_TYPE

14
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
• PROCEDURE is the reverse of the synthesis
  process.
• 1.- OUTPUTS OF FLIP-FLOPS ARE THE INTERNAL
  STATES.
• 2.- INPUT EQUATIONS TO FLIP-FLOPS DETERMINE
  NEXT INTERNAL
• STATE.
• 3.- EXCITATION TABLE IS CONSTRUCTED FROM THESE
  INPUT
• EQUATIONS TO FLIP-FLOPS. OUTPUT
  EQUATIONS ARE PRODUCED.
• 4.- THE STATE-ASSIGNED TABLE IS PRODUCED FROM
  THE EXCITATION TABLE
• 5.- THE STATE-TRANSITION TABLE IS PRODUCED BY
  ASSIGNING A STATE
• IDENTIFICATION LETTER TO EACH ASSIGNED
  STATE.
• 6.- THE STATE-TRANSITION DIAGRAM IS PRODUCED
  FROM THE STATE-
• TRANSITION TABLE.

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
15
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
• EXAMPLE ANALYZE THE FOLLOWING CIRCUIT
• Exitation equations DY1 w !y1 w y2
• 
  DY2 w y1 w y2
• 
  z y1 y2
• Next state
  equations
• 
  Y1 DY1 w !y1 w y2
• 
  Y2 DY2 w y1 w y2

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
16
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
  EXAMPLE (Continues)

Exitation equations
DY1 w !y1 wy2 DY2
w y1 w y2 z
y1 y2 Next state equations
Y1 DY1 w !y1 w y2
Y2 DY2 w y1 w y2
__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
17
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
  EXAMPLE (Continues)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
18
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
  ANOTHER EXAMPLE Analyze the following circuit

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
19
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
  ANOTHER EXAMPLE (Continues)
  
• 
  Excitation Equations
• 
  J1 w
• 
  K1 !w !y2
• 
  J2 w y1
• 
  K2 !w
• z y1 y2
• 
  
  
  

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
20
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
  ANOTHER EXAMPLE (Continues)
  
• Excitation Equations
• J1 w
• K1 !w !y2
• J2 w y1
• K2 !w
• z y1 y2
• 
  
• 
  
  
  

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
21
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
  ANOTHER EXAMPLE (Continues)
• EXCITATION TABLE
  STATE-ASSIGNED TABLE
• 
  
  
  

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
22
FINITE STATE MACHINES - II

• ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
  EXAMPLE (Continues)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
23
FINITE STATE MACHINES - II

• ALGORITHMIC STATE MACHINES (ASM) CHARTS
• DEFINITION An ASM is a type of flowchart that
  can be used to represent the state transitions
  and generated outputs for LARGE FSMs.
• THREE TYPES OF ELEMENTS
• STATE BOX, DECISION BOX, CONDITIONAL OUTPUT BOX.

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
24
FINITE STATE MACHINES - II

• ALGORITHMIC STATE MACHINES (ASM) CHARTS
  (Continues)
• Example Moore-type

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
25
FINITE STATE MACHINES - II

• ALGORITHMIC STATE MACHINES (ASM) CHARTS
  (Continues)
• EXAMPLE (Mealy-type)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
26
FINITE STATE MACHINES - II

• ALGORITHMIC STATE MACHINES
  (ASM) CHARTS (Continues)
• ANOTHER EXAMPLE (ARBITER MOORE-TYPE FSM) FSM
  THAT CONTROLS THE ACCESS BY VARIOUS DEVICES TO A
  SHARED
• RESOURCE IN A GIVEN SYSTEM. ONLY ONE DEVICE CAN
  USE THE RESOURCE AT A TIME.

27
FINITE STATE MACHINES - II

• COMPLETE FSM DESIGN EXAMPLE
• PARALLEL-TO-SERIAL CONVERTER WITH PARITY
  GENERATOR
• Word description
• Design a digital systems that will convert an
  8-bit parallel message, (b7 , b6 , b5 , b4 , b3
  , b2 , b1 , b0), composed of 7-bit ASCII
  character plus an initially set to 0 parity bit,
  into an 8-bit serial message with the correct
  parity bit set into bit b7 .

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
28
FINITE STATE MACHINES - II

• COMPLETE FSM DESIGN EXAMPLE
• PARALLEL-TO-SERIAL CONVERTER WITH PARITY
  GENERATOR
• BLOCK DIAGRAM (Data Path and Control Unit)

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
29
FINITE STATE MACHINES - II

• COMPLETE FSM DESIGN EXAMPLE
• PARALLEL-TO-SERIAL CONVERTER WITH PARITY
  GENERATOR
• STATE TRANSITION TABLE

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
30
FINITE STATE MACHINES - II

• COMPLETE FSM DESIGN EXAMPLE
• PARALLEL-TO-SERIAL CONVERTER WITH PARITY
  GENERATOR
• STATE-ASSIGNED TABLE
• CHOICE OF FLIP-FLOPS AND EXCITATION EQUATION
• Dy Y w ? y

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
31
FINITE STATE MACHINES - II

• COMPLETE FSM DESIGN EXAMPLE
• PARALLEL-TO-SERIAL CONVERTER WITH PARITY
  GENERATOR
• CIRCUIT

__________________________________________________
ECSE-323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.