4 BIT Arithmetic Logic Unit (ALU)

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4 BIT Arithmetic Logic Unit (ALU)

• Branson Ngo
• Vincent Lam
• Mili Daftary
• Bhavin Khatri
• Advisor Dave Parent
• DATE 05/17/04

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Agenda

• Abstract
• Introduction
• - Why
• - Background Information
• Project Summary
• Project Details
• - schematic
• - Layout
• - LVS report
• Longest Path Calculations
• Lessons Learned
• Summary
• Acknowledgements

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Abstract

• Our group has designed a 4 Bit Arithmetic Logic
  Unit (ALU) that can perform the following
  functions
• - NAND
• - NOR
• - XOR
• - Full Adder
• The area of our design is 1.04 x 10-7 m2
• Power IV (0.012A)(2.5V) 30mW

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Introduction

• An ALU is the fundamental unit of any computing
  system.
• Understanding how an ALU is designed and how it
  works is essential to building any advanced logic
  circuits.
• Using this knowledge and experience, we can move
  on to designing more complex integrated circuits.

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Introduction contd.
Sel1 Sel2 Output
0 0 Nand
1 0 Nor
0 1 Xor
1 1 Adder

• We have designed an ALU to handle two inputs of 4
  bits each to produce a required output based on
  the output selector line.
• The possible outputs are Nand, Nor, Xor and Sum
  as shown in the table.

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Project Summary

• The design uses the concept of parallel
  computing.
• All the different logical functional units like
  Nand, Nor, etc. are cascaded together and produce
  outputs in parallel at the Mux input.
• The benefit of this design is that all the
  computations are done in parallel and available
  simultaneously, so no clock resources are wasted.
  The Mux is then simply used to select the
  required output.

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Project Details

• There are total of 19 pin outs in our design
  including vdd and gnd.
• There are 9 D Flip-flops at the input and 4 at
  the output.
• There are 4 4x2 Muxs to select the output

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Project Details contd.

• Create Schematics and layouts for Nand, Nor, Xor,
  Adder, flip-flop, and Mux in the Cadence tool.
• Test the schematics using test bench.
• Create Schematic and layout for 1 bit ALU now
  using the schematics for the basic logical units.
• Test the schematic for 1 bit ALU.
• Create the schematic for 4 bit ALU.
• Cascade the single bit ALU layouts to create a 4
  bit ALU layout.
• Run the DRC, extracted and LVS check to verify
  the design.

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Longest Path Calculations
    Tpave 5ns/10 0.5ns Tpave 5ns/10 0.5ns Tpave 5ns/10 0.5ns    
  A 10300 A 10300 Ratio 1.705 Ratio 1.705  
   
    T pave Cg Wn ( X 10-4) Wp ( X 10-4) New Cg
1 DFF          
2 INV 0.5ns 30ff 1.5 2.55 6.91ff
3 AOI Mux 0.5ns 7ff 1.8 3.09 8.33ff
4 INV 0.5ns 8ff 1.5 2.55 7ff
5 INV 0.5ns 7ff 1.5 2.55 7ff
6 AOI XOR 0.5ns 7ff 1.5 2.55 7ff
7 INV 0.5ns 7ff 1.5 2.55 7ff
8 AOI XOR 0.5ns 7ff 1.5 2.55 7ff
9 INV 0.5ns 7ff 1.5 2.55 7ff
10 DFF        
             
             
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4 Bit ALU Schematic
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Layout
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Verification- LVS Check
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Simulation
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Simulation- Contd
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Lessons Learned

• Dont route in Poly
• Learned to fix the LVS Error
• Learn how to use Cadence tool
• Learn how to design an integrated circuit
• Make design decisions to create an efficient
  design.

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Summary

• The project taught us how to design a basic
  integrated circuit. This is a stepping stone for
  more complex circuits.
• Our project has 321 transistors and 19 terminals.
• The area of our design is 1.04 x 10-7m2
• The power is 30mW.

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Acknowledgements

• Thanks to professor David Parent for helping us
  out at all the points where we were stuck.
• Thanks to Cadence Design Systems for VLSI Lab.
• Thanks to our colleagues in the lab.