4BIT ARITHMETIC LOGIC UNIT Motorola MC5474F181

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4-BIT ARITHMETIC LOGIC UNITMotorola MC54/74F181

• Heungyoun Kim
• Lu Gao
• Jun Li
• Advisor Dr. David W. Parent
• DATE 12/05/2005

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Agenda

• Abstract
• Introduction
• Why
• Simple Theory
• Background information
• Summary of Results
• Project (Experimental) Details
• Lessons Learned
• Summary
• Acknowledgement

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Abstract

• The MC54/74F181 is a 4-bit high speed parallel
  Arithmetic Logic Unit which uses full Carry
  Lookahead for high speed arithmetic operation.
• It can perform 16 logic operations or 16
  arithmetic operations.
• We designed a 4-bit ALU that
• Operating frequency 200 MHz
• Area 340x310mm2
• Power 15.9mW

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Introduction

• The Arithmetic and Logic Unit ( ALU ) is a
  fundamental block of microprocessor.
• Design consists of different kinds of logic
  Carry Lookahead Adder, AOI, XOR, DFF, NAND, NOR,
  etc. We can practice all the circuits learned
  from the textbook.
• Strictly follow Design Flow to understand the
  Full-Custom design.
• Provide a good starting point to move on to more
  advanced IC design.

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Project Summary

• We designed a 4-bit ALU based on Motorola
  MC54/74F181 operating at 200 MHz.
• Designed the sequential logic circuit DFF.
• Total area is 340x310um2.
• Power dissipation is 15.9mW.

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Design Flow and Cost Analysis
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ALU Block Diagram with Long path
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MC54/74F181 Function Table
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Longest Path Calculations

• Start with even Tphl (5ns/(134)) for each logic
  level,  then reassign Tphl, e.g. steal time from
  inverter for XOR, to get reasonable WN and WP.
• Since AOI33 drives about 135 fF of Cg (fanout is
  8), in order to meet timing and at the same time
  get the reasonable WN and WP,  we add two
  inverters behind AOI33.

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DFF Sizing
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Schematic
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Schematic with DFF (Top-Level)
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Layout
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Verification(LVS)
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NC Verilog simulation (Logic)
S0110, A0000, B0101 ? F A?B 0101
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NC Verilog simulation (Arithmetic)
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Simulations(Logic Function)
A3A2A1A0 1010 B3B2B1B0 1001 M1 Cin1 --------
------------------- S3S2S1S0 1111 F A
1010 S3S2S1S0 1010 F B 1001 S3S2S1S0
0101 F B 0110 S3S2S1S0 0000 F A 0101
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Simulations(Arithmetic Function)
A3A2A1A0 1010 B3B2B1B0 1001 M0 Cin1 --------
--------------------- S3S2S1S0 1111 F A minus
1 1001 S3S2S1S0 1010 F (AB) plus AB 0110
S3S2S1S0 0101 F (AB) plus AB
1101 S3S2S1S0 0000 F A 1010
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POWER
Power 47.77 mW / 3 clocks 15.9 mW
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Lessons Learned

• Organize data and keep track of schedule.
• Use cell based design and uniform cell height.
• Draw a floor plan including route of power and
  major signals before you layout.
• Do DRC often and LVS for each cell.

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Summary

• Our design met all the specifications, speed 200
  MHz, area 340 x 310 µm2, and power dissipation
  15.9mW.
• Learned how to design, simulate and implement
  static CMOS circuits with delay constraint in
  transistor level using the AMI06 process.
• Theory and CDS tool experience learned through
  this project would be a great stepping stone to
  the upper level design project and career.

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Acknowledgements

• Thanks to our families for all their support.
• Thanks to Prof. David W. Parent for his help.
• Thanks to Cadence Design Systems for the VLSI
  lab.
• Thanks to Hummingbird for the great remote login.