DIGITAL SIGNAL PROCESSOR

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DIGITAL SIGNAL PROCESSOR
BY
MURALIMOHAN VINOD KUMAR BANSAL JAYRAM
SATYA KIRAN AMARENDER REDDY SUDHANSU
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ACHIEVED FEATURES

• 16 bit address lines - Capable of addressing 64kB
• 14 General Purpose Registers
• Flexible and Orthogonal Instruction set
• All GPR can be used as Address Registers
• Auto increment and Auto decrement mode
• Bit Reverse address generation capability through
  BR instruction
• Wide instruction set with 28 distinct opcodes
• Includes Special instructions such as
  ADDL,BR,ADC,SBB
• Radix-2 FFT can be implemented efficiently

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ROUTING OF DSP
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INSTRUCTION SET
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BIT REVERSAL CIRCUIT
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LAYOUT OF BIT REVERSAL CIRCUIT
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SHIFTER
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MULTIPLIER
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MULTIPIER
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1 BIT ALU
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D FLIPFLOP
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D FLIPFLOP
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ALU 1 BIT
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4to1 ONE BIT MUX
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PART OF INC/DCR CIRCUIT
OUTPUT
FA
FA
FA
FA
FA
FA
FA
FA
INCR
DCR
8 BIT INPUT DATA
INCR
DCR
OUTPUT
ALU CARRY
0 0 1
increment of MSB 0 1
X decrement 1
0 X
increment 1 1 X
pass
TRUTH TABLE OF INCR/DCR
16
16 bit output
ALU CARRY
INCR
8 bit adder
8bit adder
comb.ckt
INCR
DCR
16 bit input
16 BIT INCR/DCR
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FROM REG FILE
FROM REG FILE
MAR
MAR WITH INCR/DCR
ADDRESS BUS
ADDRESS BUS
INCR/DCR
TO REG FILE
TO REG FILE
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MARINCR/DCR
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REG-H/L ARRAY
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CONTROL UNIT
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PROCESSOR