Chapter 1: Computer System Overview

1
Chapter 1 Computer System Overview

• CS 472 Operating Systems
• Indiana University Purdue University Fort Wayne

2
The operating system (OS) . . .

• Is a resource manager for a computer system
• Manages one or more processors
• Manages memory
• Manages secondary memory
• Disk drives
• Tape
• Removable drives
• Manages other I/O devices
• Provides a set of services to system users

3
Basic computer system elements

• Processor
• Main Memory
• volatile
• also referred to as real memory or primary memory
• I/O modules
• secondary memory devices
• communications equipment
• terminals
• System bus
• Provides communication among processors, memory,
  and I/O modules

4
Top-Level components
5
Processor

• Two internal registers for memory I/O
• Memory address register (MAR)
• Specifies the address for the next read or write
• Memory buffer register (MBR)
• Contains data written into memory or receives
  data read from memory
• Two more for each I/O port
• I/O address register
• I/O buffer register

6
Other processor registers

• User-visible registers
• Enable programmer to minimize main-memory
  references by optimizing register use
• Control and status registers
• Used by processor to control operation of the
  processor
• Used by privileged operating-system routines to
  control the execution of programs

7
User-visible registers

• May be referenced by assembly/machine language
• Available to all programs
• application programs and system programs
• Types of registers
• Data
• Address
• Index
• Segment pointer
• Stack pointer

8
User-visible registers

• Address Registers
• Index
• Involves adding an index to a base value to get
  an address
• Segment pointer
• When memory is divided into segments, memory is
  referenced by a segment and an offset
• Stack pointer
• Points to top of the system stack

9
Control and status registers

• Program Counter (PC)
• Contains the address of an instruction to be
  fetched
• Instruction Register (IR)
• Contains the instruction most recently fetched
• Program Status Word (PSW)
• Condition codes
• Interrupt enable / disable
• Supervisor / user mode
• Etc.

10
Control and status registers

• Condition Codes or Flags
• Bits set by the processor hardware as a result of
  operations
• Examples
• Positive result
• Negative result
• Zero
• Overflow

11
The fetch / execute cycle

• The processor fetches the instruction from memory
• Program counter (PC) holds address of the
  instruction to be fetched next
• Fetched instruction is placed in the instruction
  register (IR)
• Program counter is incremented after each fetch
• Processor then executes instruction in the IR

12
Categories of instructions

• Processor-memory
• Transfer data between processor and memory
• Processor-I/O
• Data transferred to or from a peripheral device
• Data processing
• Arithmetic or logic operation on data
• Control
• Alter sequence of execution

13
Interrupt

• . . . a signal from a device to the processor
  that interrupts the normal sequence of processor
  activity
• Processor checks for the signal at the end of
  each fetch/execute cycle
• If no interrupt, fetch the next instruction for
  the current program
• Otherwise . . .
• Suspend execution of the current program
• Send ACKnowlegement to allow the device to remove
  the signal
• Execute the interrupt handler routine
• Effect is like an unscheduled call to the
  interrupt handler

14
Interrupt handler

• An interrupt handler . . .
• Is part of the operating system
• Is specific to the device causing the interrupt
• Typically returns to the interrupted process
• This is usually transparent to the user program

15
Interrupt

• Suspends the normal sequence of execution

16
Interrupt cycle
17
Simple interrupt processing
18
Flow of control in a program with I/O
19
Multiple interrupt handling

• What if an interrupt occurs while an interrupt
  handler is running?
• Two ways to deal with this
• Disable interrupts while the handler runs
• Define priorities for interrupts

20
Disable interrupts while handler runs
21
Define priorities for interrupts
22
Define priorities for interrupts
middle priority interrupt
23
Classes of interrupts

• Program generated interrupts are often called
  faults or traps

24
Multiprogramming

• More than one process is active on a single
  processor
• There is a ready queue of processes waiting for
  the processor
• A process must wait after making an I/O request
  or after a timer interrupt

I/O request
running
blocked
timer
wake-up
dispatch
ready
25
Memory hierarchy

• Faster access time
• greater cost per bit
• Greater capacity
• smaller cost per bit
• slower access speed

26
Going down the hierarchy

• Decreasing cost per bit
• Increasing capacity
• Increasing access time
• Decreasing frequency of access of the memory by
  the processor

27
Secondary memory

• Managed by the operating system
• Nonvolatile
• Auxiliary memory
• Used to store program and data files

28
Cache memory

• Invisible to the operating system
• Faster than main memory
• Exploits the principle of locality

29
Cache memory

• Contains a copy of a portion of main memory
• Processor first checks cache
• If not found in cache, the block of memory
  containing the needed information is moved to the
  cache and delivered to the processor

30
I/O module

• Is an interface between the bus and a device
• Hides the complexity of the device from the
  processor
• The processor issues commands to an I/O module
• The I/O module controls the device to perform the
  requested action
• It also buffers data and maintains a status
  register that the processor can read

31
Techniques for performing I/O

• Programmed I/O
• Interrupt-driven I/O
• Direct memory access (DMA)

32
Programmed I/O

• I/O module performs the requested action
• No interrupts occur
• Module sets appropriate bits in the I/O status
  register
• Processor checks status until operation is
  complete
• Processor does a busy-wait for each character

33
Interrupt-driven I/O

• Processor is interrupted when I/O module ready to
  exchange data
• Processor saves context of program executing and
  begins executing interrupt-handler
• No needless waiting
• Involves much processor overhead because . . .
• Every character read or written passes through
  the processor
• One interrupt for each character

34
Direct memory access (DMA)

• Transfers an entire block of data directly to or
  from memory
• An interrupt is sent when the transfer of the
  entire block is complete
• One interrupt per block of data

35
Direct memory access (DMA)

• A DMA controller transfers data directly between
  a device (typically a disk) and memory
• The data does not pass through the processor
• The I/O module has authority to read from or
  write to memory
• This relieves the processor responsibility for
  the exchange
• The DMA competes with the processor for memory
  access
• This is known as cycle stealing
• Although cycle stealing halts the processor, this
  is not an interrupt

36
Peripheral processor (or I/O channel)

• This is a special DMA similar to the CPU
• Has its own fetch/execute cycle
• Runs a channel program out of memory just like
  the CPU runs programs
• The channel program can perform more complicated
  I/O than simple block transfer