Daniel Parker, Chris Ridenour

1
AUV 2008 - Sonar Reciever
Daniel Parker, Chris Ridenour
dkp031000_at_utdallas.edu, car032000_at_utdallas.edu
Department of Electrical Engineering Erik Jonsson
School of Engineering Computer
Science University of Texas at Dallas Richardson,
Texas 75083-0688, U.S.A.
Project Results
Project Goals

• Memory Map Interface Between FPGA and AVR
• VHDL written for ADC interface and FIR filter
  implementation.
• Circuit Card layouts for ADC and Level Converter
  Boards for testing
• and debugging VHDL code on FPGA

• Implement a sonar receiver on an FPGA
• Develop a Memory Map interface for the FPGA
• Enable communication between an ADC and the FPGA
• Develop and Implement a FIR Filter on the FPGA
• Develop a correlation block for the FPGA
• Design a circuit board to contain the entire
  sonar receiver

Project Overview

• The Sonar Receiver operates in the following
  manner
• Hydrophones detect a sonar ping
• Transducers converts that sound energy to an
  analog
• electrical signal
• ADCs convert the analog signals to digital ones
  and
• passes then to the FPGA
• FPGA performs FIR filtering on the signals, then
  processes
• them through a correlator to determine the Time
  Difference
• Of Arrival (TDOA) of the signals.
• FPGA then passes the TDOA information to the CPU
  through
• a microprocessor.
• The CPU then uses the TDOA information to
  determine the
• bearing and elevation of the target pinger in
  passive mode,
• or the distance to the bottom of the tank in
  active mode.

Level Converter Board
ADC Board
Project Conclusions/Outcomes

• Integrate ADC interface and FIR filter into VHDL
  code
• Write and integrate correlation block into VHDL
  code
• Implement completed VHDL code onto an FPGA
• Design and print a circuit card that contains the
  entire sonar receiver
• Test and integrate completed sonar receiver board
  into the AUV