Wakerly Chapter 5

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Wakerly Chapter 5

• HDLs in particular VHDL

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History of Digital Design

• 1975 primary tools were logic-drawing template,
  a ruler, and a pencil!
• 1980s schematic editor software
• But HDLs were emerging
• Layout editors also used for those who design at
  transistor level, myself included
• 1990s accelerated use of HDLs since PLDs and
  FPGAs become cheap and common
• Schematics often used only to specify board-level
  interconnections among these devices

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First HDL PALASM

• Name stands for PAL Assembler
• Was not high-level like assembly language
• Invented in early 80s by Monolithic Memories,
  Inc., inventors of the PAL device
• Was used just for PAL devices

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Subsequent languages

• Soon competing languages emerge CUPL, ABEL
• Have if-then-else, case, and ability to derive
  logic expressions from high-level constructs
• VHDL, Verilog started out as simulation
  languages!
• Thus many languages features have roots in
  simulation applications
• But soon people discovered that a subset of these
  languages are good for hardware design as well

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VHDL features

• Designs can be decomposed hierarchically
• Each design element has
• A well-defined interface for connecting with
  other elements
• Precise functional description (for simulation)
• Functional description may be
• Behavioral algorithm (direct functional
  description)
• Hardware structural description (such as in terms
  of gates and their interconnections)

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VHDL features (contd)

• Concurrency, timing, and clocking can all modeled
  in great detail (and complication!)
• The complexing timing models scare many people
  away from VHDL. But to know enough VHDL just to
  describe a circuit is really not so bad.
• The logical operation and timing behavior of a
  design can be simulated

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VHDL Program Structure

• VHDL was designed with structured programming in
  mind
• Borrowed concepts from Pascal and ADA
• Actually VHDL is almost object-oriented
• Has separate interface and implementation parts!
• But, doesnt have classes with which to
  instantiate new objects with. Needs an update!

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VHDL Structure Entity and Architecture

• Entity simply a declaration of a modules inputs
  and outputs.
• Like an interface. (CS)
• Like a wrapper and a hook. (Wakerly)
• Architecture a detailed description of whats
  inside a module. Like an implementation.
• You need both parts.
• You can have multiple implementations for each
  interface, but must statically bind some unique
  implementation with each interface

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A simple example (already seen a MUX in Chapter
1, remember?)
entity Inhibit is -- a.k.a. but-not as in X
but not Y port (X,Y in BIT
Z out BIT end Inhibit -- end of
entity declaration architecture Inhibit_arch of
Inhibit is begin Z lt 1 when X1 and
Y0 else 0 end Inhibit_arch -- end of
architecture declaration
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Syntax of VHDL entity declaration
entity entity-name is port (signal-names
mode signal-type signal-names mode
signal-type signal-names mode
signal-type) -- careful here! end entity-name
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Some explanation

• Signal-names comma-separated list of 1 or more
  user-selected identifiers to name
  external-interface signals
• Mode signal direction
• in, out, buffer (output which is also readable
  inside entitys architecture), inout (often used
  for 3-state i/o pins)
• Signal-type built-in or user-defined signal
  type. Later.

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Syntax of VHDL architecture definition
architecture arch-name of entity-name is type
declarations signal declarations constant
declarations function definitions procedure
definitions component declarations begin
concurrent-statements end arch-name
named wires
later
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types

• A type is the set of values
• Every signal, variable, and constant in VHDL has
  a type
• To each type theres typically also an associated
  set of operators (add, AND, etc.).
• VHDL has just a few predefined types.
• The only ones well see here are integer,
  character, and boolean
• There are also built-in types bit and bit_vector,
  but the user-defined types std_logic and
  std_logic_vector are more useful (IEEE 1164 std)
• Subtyping is allowed (only subranges, please!)
• Theres more stuff in book (pp 262-263)

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Array types
General syntax of array typedef

• type type-name is array (start todownto end) of
  element-type
• type type-name is array (range-type) of
  element-type etc.

Examples of array typedef
type byte is array (7 downto 0) of
STD_LOGIC constant WORD_LEN integer
32 type word is array (WORD_LEN-1 downto 0 of
STD_LOGIC
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Accessing array elements

• Use array name and the index in parentheses
• M(11), W(WORD_LEN-5), R(1,0)
• A 2-d array is just an array of 1-d arrays
• Can also specify values by index, like this
• W (0gt0, 8gt0, 16gt0, 24gt0,
• othersgt1)

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Another way of writing array literals of a
STD_LOGIC array
Use a string, like so W
11111110111111101111111011111110 -- same
as previous example!
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The most important array type in typical VHDL
programs!

• Thats the IEEE 1164 std user-defined logic type
  std-logic-vector
• This defines an ordered set of std_logic bits
• Heres the def of the type

type STD_LOGIC_VECTOR is array (natural range lt
gt) of STD_LOGIC

• an example of an unconstrained array type
• The range of the array is unspecificed, except
  that it must be a subrange of a defined type, in
  this case, natural (0, 1, 2,).
• Actual range is specified when a signal or
  variable is assigned this type

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functions

• See syntax in Table 5-22, p. 266
• Example, Table 5-23, p. 266 but-not gate using a
  function.
• See next slide

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But-not gate using a function
architecture Inhibit_archf of Inhibit is function
ButNot (A,B bit) return bit is begin if B
0 then return A else return 0 end
if end ButNot begin Z lt ButNot(X,Y) end
Inhibit_archf
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Libraries and packages

• LIBRARY a place where VHDL compiler stores
  information about a particular design project
• Intermediate files used in the analysis,
  simulation, synthesis of design
• Library location is implementation-dependent
• For each design, the compiler automatically
  creates and uses a library named work
• When compiler analyzes each file in the design,
  it puts the results there.
• Other libraries may also be used.
• Common libraries shared by various designs
• Standard libraries such as ieee, Xilinxs unisim

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Library statement in VHDL source

• library ieee -- needed if you want to use
  the ieee library
• library unisim -- will see this in
  Xilinx-generated files
• library work -- implicitly included in the
  beginning of every VHDL file

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packages

• Specifying a library name in a design gives it
  access to any previously analyzed entities and
  architectures stored in the library
• But it doesnt give access to type definitions
  and the like
• This is what packages and use clauses are for

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Whats in a package?

• A package is a file containing definitions of
  objects that can be used in other programs
• Is an ADA concept
• Like the entity-architecture pair, the package is
  another precursor to the OOP idea!
• object here means signals, types, constants,
  functions, procedures, components declarations,
  etc. NOT objects as in OOP.

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Using a package

• The things in a pkg is global
• Available to any VHDL entity that uses the
  package
• Types and constants defined in a pkg are known in
  any file that uses the pkg
• Functions and procedures defined in apkg can be
  called in files that use the pkg
• To use a package you say use. for example
• use ieee.std_logic_1164.all -- use all
  definitions in pkg
• use ieee.std_logic_1164.std_ulogic -- use just
  def std_ulogic type

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Structural design elements

• Finally ready to look at the guts of a VHDL
  design, the executable part of the code!
• Recall that the body of an architecture is a
  series of concurrent statements
• Each one of these execute simultaneously with the
  other ones in the same architecture body
• Quite different from a typical software
  program!!!
• If the last stmt updates a signal thats used by
  the first stmt (as input), then the simulator
  will go back to the first stmt and update its
  results accordingly!!

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Kinds of concurrent statements in VHDL

• VHDL has different kinds of concurrent statements
• Component statements
• Concurrent signal assignment statements
• Process statements
• Also has ways of bundling a set of sequential
  statements to operate as a single concurrent
  statement
• These statements give rise to 3 somewhat distinct
  styles of circuit design and description!

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Component statements(most important to us
because thats what we see from Xilinx)