Introduction to Sequential Logic Design

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Introduction to Sequential Logic Design
Bistable elements
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Sequential Systems

• A combinational system is a system whose outputs
  depends only upon its current inputs.
• A sequential system is a system whose output
  depends on current input and past history of
  inputs.
• All systems we have looked at to date have been
  combinational systems.

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Sequential Circuits

• Outputs depends on the current inputs and the
  systems current state.
• State embodies all the information about the
  past needed to predict current output based on
  current input.
• State variables, one or more bits of information.

The state is a collection of state variables
whose values at any one time contain all the
information about the past necessary to account
for the circuits future behavior. Herbert
Hellerman, Digital Computer Systems Principles
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Describing Sequential Circuits

• State table
• For each current-state, specify next-states as
  function of inputs
• For each current-state, specify outputs as
  function of inputs
• State diagram
• Graphical version of state table
• More on this next week

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Finite State Machine

• A circuit with n binary state variables has 2n
  possible states, which is always finite, so
  sequential circuits are sometimes called
  Finite-State Machines (FSM).
• For most sequential circuits, the state changes
  occur at times specified by a free-running clock
  signal.
• Clock is active high state changes occur ar
  rising edge, or when the clock is HIGH
• Clock is active low falling edge, or when LOW
• Feedback sequential circuit uses ordinary gates
  and feedback loops to obtain memory, create build
  blocks
• Clocked synchronous state machine uses above
  building blocks to create circuit.

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Clock signals

• Very important with most sequential circuits
• State variables change state at clock edge.

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Bistable element

• The simplest sequential circuit, no way to
  control its state.
• Two states
• One state variable, say, Q, two possible states

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Analog analysis

• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V

2.5 V
2.5 V
2.51 V
5.0 V
0.0 V
2.5 V
2.5 V
4.8 V
0.0 V
5.0 V
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Metastability

• Metastability is inherent in any bistable circuit
• Two stable points, one metastable point

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Another look at Metastability
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Why all the harping on metastability?

• All real systems are subject to it
• Problems are caused by asynchronous inputs that
  do not meet flip-flop setup and hold times.
• Details in Chapter-7 flip-flop descriptions and
  in Section 8.9 (later in course ECE4110).
• Especially severe in high-speed systems
• since clock periods are so short, metastability
  resolution time can be longer than one clock
  period.
• Many digital designers, products, and companies
  have been burned by this phenomenon.

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Back to the bistable.

• How to control it?
• Control inputs

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Back to the bistable.

• How to control it?
• Control inputs
• S-R latch

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Terminology

• A bistable memory device is the generic term for
  the elements we are studying.
• Latches and flip-flops (FFs) are the basic
  building blocks of sequential circuits.
• latch bistable memory device with level
  sensitive triggering (no clock), watches all of
  its inputs continuously and changes its outputs
  at any time, independent of a clocking signal.
• flip-flop bistable memory device with
  edge-triggering (with clock), samples its inputs,
  and changes its output only at times determined
  by a clocking signal.
• Warning some authors use the terminology
  Flip-Flop and Clocked Flip-Flop instead of latch
  and Flip-Flop
• latch, flip-flop more standard

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Next

• Latches and flip-flops
• Read Ch-7.2
• HW 11 (Last homework)
• Assign Fri. 12/02/2004 Work Wakerly problems
  7.2, 5, 7,18,26.            Due Fri.
  12/09/2004.