Chapter 1 Design Partitioning and Phases

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Chapter 1Design Partitioning and Phases
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Outline

• Design Partitioning
• Design Phases
• Architecture/spec
• Microarchitecture
• Logic Design (VHDL/Verilog)
• Circuit Design (transistor level analog design)
• Physical Design (layout)
• Fabrication, Packaging, Testing
• Testing, characterization, qualification

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Coping with Complexity

• How to design System-on-Chip?
• Many millions (soon billions!) of transistors
• Tens to hundreds of engineers
• Structured Design
• Design Partitioning

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Structured Design

• Hierarchy Divide and Conquer
• Break system into modules/blocks
• Regularity
• Reuse modules wherever possible (IP reuse)
• Ex Standard cell library
• Use slices
• Modularity well-formed interfaces
• Allows modules to be treated as black boxes

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Design Partitioning

• Spec/Architecture/MRD Users perspective, what
  does it do? (system architect/marketing role)
• High-level system view (input/output view)
• Microarchitecture (lead designer/system architect
  role)
• Partitions the system architecture into
  functional blocks with registers
• Logic how are functional blocks constructed
  (digital designer role)
• Usually RTL code (VHDL/Verilog) implementation of
  the blocks.
• Circuit how are circuits implemented (analog
  designer role)
• Custom transistor design
• Physical chip layout (physical designer role)
• Custom and PR

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Gajski Y-Chart
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Logic Design Using HDLs

• Hardware Description Languages
• Widely used in logic design
• Verilog and VHDL
• Describe hardware using code
• Document logic functions (block spec)
• Simulate logic before building
• Synthesize code into gates and layout
• Requires a library of standard cells
• Good enough for many low-speed applications

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Circuit Design

• Transistor level implementation
• Standard cell library implementation (NANDs,
  NORs, ANDs, Ors, etc.)
• Custom circuit implementation (example are
  high-speed Interfaces (SerDes), A/D, D/A
  converters, PLLs, etc.)
• Focus on optimizing the block for speed, area,
  power

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Example Carry Logic

• cout (ab) (ac) (bc)
• Logic implementation

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Example Carry Logic

• cout (ab) (ac) (bc)
• Transistor level implementation

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Gate-level Netlist
module carry(input a, b, c, output
cout)   wire x, y, z   and g1(x, a, b) and
g2(y, a, c) and g3(z, b, c) or g4(cout, x,
y, z) endmodule
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SPICE Netlist

• .SUBCKT CARRY A B C COUT VDD GND
• MN1 I1 A GND GND NMOS W1U L0.18U AD0.3P
  AS0.5P
• MN2 I1 B GND GND NMOS W1U L0.18U AD0.3P
  AS0.5P
• MN3 CN C I1 GND NMOS W1U L0.18U AD0.5P AS0.5P
• MN4 I2 B GND GND NMOS W1U L0.18U AD0.15P
  AS0.5P
• MN5 CN A I2 GND NMOS W1U L0.18U AD0.5P
  AS0.15P
• MP1 I3 A VDD VDD PMOS W2U L0.18U AD0.6P AS1 P
• MP2 I3 B VDD VDD PMOS W2U L0.18U AD0.6P AS1P
• MP3 CN C I3 VDD PMOS W2U L0.18U AD1P AS1P
• MP4 I4 B VDD VDD PMOS W2U L0.18U AD0.3P AS1P
• MP5 CN A I4 VDD PMOS W2U L0.18U AD1P AS0.3P
• MN6 COUT CN GND GND NMOS W2U L0.18U AD1P AS1P
• MP6 COUT CN VDD VDD PMOS W4U L0.18U AD2P AS2P
• CI1 I1 GND 2FF
• CI3 I3 GND 3FF
• CA A GND 4FF
• CB B GND 4FF
• CC C GND 2FF
• CCN CN GND 4FF

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Physical Design

• Floorplan
• Standard cells
• Place route
• Custom transistor layout
• Area estimation

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Example Floorplan
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Example Layout
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Standard Cells

• Uniform cell height
• Uniform well height
• M1 VDD and GND rails
• M2 Access to I/Os
• Well / substrate taps
• Exploits regularity

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Synthesized Controller Example

• Synthesize HDL into gate-level netlist
• Place Route using standard cell library

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Area Estimation

• Need area estimates to make floorplan
• Compare to another block you already designed
• Or estimate from transistor/gate counts
• Budget room for large wiring tracks (the higher
  the utilization, the harder to achieve timing
  closure).

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Design Verification

• Fabrication is slow expensive
• State of the art 1M, 3 months
• Debugging chips is very hard
• Limited visibility into operation
• Prove design is right before building!
• Logic simulation
• Ckt. simulation / formal verification
• Layout vs. schematic comparison
• Design electrical rule checks
• Verification is gt 50 of effort on most chips!

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Fabrication Packaging

• Tapeout final layout
• Fabrication
• 6, 8, 12 wafers
• Optimized for throughput, not latency (10 weeks!)
• Cut into individual dice
• Packaging
• Wire-bond, flip-chip options

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Testing/Characterization/Qualification

• Tests/validation done after fabrication before
  release to manufacturing
• Sample screening with manufacturing tests using
  vectors generated by the design team. Vectors are
  generated using DFT- Design for Test) (Test
  engineer role)
• Lab functional validation (Application engineer
  role)
• Test for extreme corners (characterization for
  PVT) (Test engineer role)
• Qualification/reliability (Temperature cycling,
  HTOL) (Test/product engineer role)

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Chapter 2 MOS Transistor Theory
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Outline

• MOS Capacitor
• nMOS I-V Characteristics
• pMOS I-V Characteristics
• Gate and Diffusion Capacitance
• Pass Transistors
• RC Delay Models
• Operation and Modeling of the MOS transistor by
  Yannis Tsividis is a good reference

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MOS Capacitor

• Gate and body form MOS capacitor
• Operating modes
• Accumulation
• Depletion
• Inversion

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Terminal Voltages

• Mode of operation depends on Vg, Vd, Vs
• Vgs Vg Vs
• Vgd Vg Vd
• Vds Vd Vs Vgs - Vgd
• Source and drain are symmetric diffusion
  terminals
• By convention, source is terminal at lower
  voltage
• Hence Vds ? 0
• nMOS body is grounded. First assume source is 0
  too.
• Three regions of operation
• Cutoff
• Linear
• Saturation

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nMOS Cutoff

• Vgs lt Vt
• No channel
• Ids 0

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nMOS Linear

• Channel forms
• Current flows from d to s
• e- from s to d
• Ids increases with Vds
• Similar to linear resistor

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nMOS Saturation

• Channel pinches off near the drain
• Ids independent of Vds
• We say current saturates
• Similar to a current source (Ids becomes
  independent of Vds)

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I-V Characteristics

• In Linear region, Ids depends on
• How much charge is in the channel?
• How fast is the charge moving?

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Channel Charge

• MOS structure looks like parallel plate capacitor
  while operating in inversion
• Gate oxide channel
• Qchannel

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Channel Charge

• MOS structure looks like parallel plate capacitor
  while operating in inversion
• Gate oxide channel
• Qchannel CV (charge on a plate of a capacitor)
• C gate-to-channel capacitor

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Channel Charge

• MOS structure looks like parallel plate capacitor
  while operating in inversion
• Gate oxide channel
• Qchannel CV
• C Cg eoxWL/tox CoxWL
• V

Cox eox / tox
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Channel Charge

• MOS structure looks like parallel plate capacitor
  while operating in inversion
• Gate oxide channel
• Qchannel CV
• C Cg eoxWL/tox CoxWL
• V Vgc Vt (Vgs Vds/2) Vt

Cox eox / tox
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Carrier velocity

• Charge is carried by e- due to the electric field
• Carrier velocity v proportional to lateral
  E-field between source and drain
• v

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Carrier velocity

• Charge is carried by e-
• Carrier velocity v proportional to lateral
  E-field between source and drain
• v mE m called mobility
• E

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Carrier velocity

• Charge is carried by e-
• Carrier velocity v proportional to lateral
  E-field between source and drain
• v mE m called mobility
• E Vds/L
• Time for carrier to cross channel
• t

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Carrier velocity

• Charge is carried by e-
• Carrier velocity v proportional to lateral
  E-field between source and drain
• v mE m called mobility
• E Vds/L
• Time for carrier to cross channel
• t L / v

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nMOS Linear I-V

• Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross

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nMOS Linear I-V

• Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross

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nMOS Linear I-V

• Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross

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nMOS Saturation I-V

• If Vgd lt Vt, channel pinches off near drain
• When Vds gt Vdsat Vgs Vt
• Now drain voltage no longer increases current

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nMOS Saturation I-V

• If Vgd lt Vt, channel pinches off near drain
• When Vds gt Vdsat Vgs Vt
• Now drain voltage no longer increases current

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nMOS Saturation I-V

• If Vgd lt Vt, channel pinches off near drain
• When Vds gt Vdsat Vgs Vt
• Now drain voltage no longer increases current

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nMOS I-V Summary

• Shockley 1st order transistor models

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Example

• 0.6 mm process from AMI Semiconductor
• tox 100 Å
• m 350 cm2/Vs
• Vt 0.7 V
• Ids vs. Vds
• Vgs 0, 1, 2, 3, 4, 5
• Use W/L 4/2 l

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pMOS I-V

• All dopings and voltages are inverted for pMOS
• Mobility mp is determined by holes
• Typically 2-3x lower than that of electrons mn
• Thus pMOS must be wider to provide same current
• In this class, assume mn / mp 2

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Second-order Effects

• Velocity Saturation For large Vds (I.e., high
  lateral electric field in the channel), carrier
  velocity ceases to increase linearly with
  electric field resulting in reduced Ids.
• Mobility degradation For large Vgs (I.e., high
  vertical vertical field), carrier mobility is
  reduced due to surface scattering resulting in
  reduced Ids.
• Channel length modulation Ids increases
  slightly with Vds in saturation.
• Body Effect Threshold voltage increases with
  the potential difference between source and body
  Vsb.
• Subthreshold Conduction (weak inversion) Below
  threshold voltage Ids drops off exponentially.
  This undesired leakage is the major source of
  static power consumption in sub-micron CMOS
  technologies.
• Junction Leakage Reverse biased source/drain
  junction diodes conduct a small current.
• Gate Leakage In modern technologies with thin
  oxides, carrier tunneling through the gate
  results in undesired current.
• Mobility and threshold voltage decrease with
  increasing temperature resulting in degraded
  transistor performance.

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Capacitance

• Any two conductors separated by an insulator have
  capacitance
• Gate to channel capacitor is very important
• Creates channel charge necessary for operation
• Source and drain have capacitance to body
• Across reverse-biased diodes
• Called diffusion (or depletion )capacitance
  because it is associated with source/drain
  diffusion

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Gate Capacitance

• Approximate channel as connected to source
• Cgs Cg eoxWL/tox CoxWL CpermicronW
• Cpermicron is typically about 1.5-2 fF/mm

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Diffusion Capacitance

• Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
• Use small diffusion nodes
• Comparable to Cg
• for contacted diff
• ½ Cg for uncontacted
• Varies with process

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Effective Resistance

• Shockley models have limited value
• Not accurate enough for modern transistors
• Too complicated for much hand analysis
• Simplification treat transistor as resistor
• Replace Ids(Vds, Vgs) with effective resistance R
• Ids Vds/R
• R averaged across switching of digital gate
• Too inaccurate to predict current at any given
  time
• But good enough to predict RC delay

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RC Delay Model

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

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RC Values

• Capacitance
• C Cg Cs Cd 2 fF/mm of gate width
• Values similar across many processes
• Resistance
• Improves with shorter channel lengths
• Unit transistors
• Defined as a minimum contacted device (4/2 l)

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

d 6RC