Microelectronic Design Technology

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CHAPTER 5
Microelectronic Design Technology
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Classifications of Integrated Circuits
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Implementation choices
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ASICs vs. FPLDs ( pizza equivalent)
Full-custom ASIC Prepare pizza sauce, toppings,
dough from scratch takes a long
time Standard-cell-based ASIC Choose from
limited selection of toppings and dough less
work but still slow Gate-array-based ASIC Add
canned toppings to pre-cooked crusts save some
time and cost Field-programmable logic device
Frozen pizza limited selection, trivial
to cook, very cheap
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ASIC Design Methodologies
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ASIC Design Flow
1.Design entry. Using a hardware description
language (HDL) or schematic entry. 2. Logic
synthesis. Produces a netlistlogic cells and
their connections. 3. System partitioning. Divide
a large system into ASIC-sized pieces. 4.
Prelayout simulation. Check to see if the design
functions correctly. 5. Floorplanning. Arrange
the blocks of the netlist on the chip. 6.
Placement. Decide the locations of cells in a
block. 7. Routing. Make the connections between
cells and blocks. 8. Extraction. Determine the
resistance and capacitance of the
interconnect. 9. Postlayout simulation. Check to
see the design still works with the added loads
of the interconnect.
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ASIC Design Flow
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Full-Custom Design Methodology
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Full-Custom Design Methodology
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Standard-Cell Based Design Methodology
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Gate-Array Based Design Methodology

• This approach is faster than the standard-cell
  based approach because part of the
  fabrication process has been complete.

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Gate-Array Based Design Methodology
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FPGA Based Design Methodology

• This approach has extremely fast turn-out time
  since FPGA devices has been fabricated.

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Comparison of Design Methodologies
Full-custom design Standard-cell based design Gate-array based design FPGA-based design
Speed -
Integration density --
High-volume device cost
low-volume device cost --- --
Custom mask layer All All Some None
Fabrication time --- -- -
Time to Market --- --
Risk reduction --- -- -
Future design modification --- -- -
desirable - not desirable
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Why do we want FPGAs

• Advantages of using FPGAs

• Fast turn-out time

• The ability of re-programming

• The capability of dynamic reconfiguration

• FPGA Applications

• Ideal platform for prototyping

• Providing fast implementation to reduce
  time-to-market

• Cost effective solutions for products with
  small volumes on demand

• Implementing hardware systems requiring
  re-programming flexibility

• Implementing dynamically re-configurable systems

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Design Constraints for Digital ICs
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How to Find Circuits Complying with Design
Constraints
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Example How to Search a Proper Circuit
Implementation in FPGA Design Flow

• Given Logic Function

• This circuit is either from schematic
  capture or from logic synthesis

• FPGA Library Components

• The library contains five components
• Three inverters at size 1, 3, 5
• Two two-input NAND gates at size 1 and 3

• Design Constraints

• The maximum delay between an input and an output
  should not exceed 5 ns

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Example How to Search a Proper Circuit
Implementation in FPGA Design Flow

• Step 1 Use the available logic gates to
  implement the given function.

(Technology Mapping)

• Step 2 Select proper size for each gate used in
  the above circuit.

(Gate Sizing)

• After this step, the circuit can be
  simulated to verify that it complies with
  timing constraints.
• In the simulation, the parasitic
  capacitance and resistance on interconnects
  are estimated (Estimated wire load)

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Example How to Search a Proper Circuit
Implementation in FPGA Design Flow

• Step 3 Determine where to place these gates and
  how to connect them (Placement
  Routing).

• Some algorithms first place the components
  and then route the interconnects.
• Some algorithms perform the placement and
  routing simultaneously

• Steps 1, 2, and 3 are included in the
  implementation phase of the FPGA design Flow

• Step 4 Perform post-layout simulation to verify
  that the generated circuit
  complies with timing constraints

• Since detail information of each interconnect is
  available, the circuit can be simulated with
  accurate wire load.
• The process that writes the accurate wire load
  into the circuit netlist is called back
  annotation

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Programmable Logic Devices (PLDs)
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Programmable Logic Devices (PLDs)

• Standard ICs, available in standard
  configurations, sold in high volume
• No customized cells or masks, just a single large
  block of programmable interconnect
• Can be configured / programmed to
• create a specialized device
• Fast turn-around time
• Examples
• Mask-programmable ROM programmed when ordered
• Programmable ROM programmed electrically,
  erased electrically or using ultraviolet light,
  all by customer

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Definitions

• Field Programmable Device (FPD)

• a general term that refers to any type of
  integrated circuit used for implementing digital
  hardware, where the chip can be configured by the
  end user to realize different designs.
  Programming of such a device often involves
  placing the chip into a special programming unit,
  but some chips can also be configured
  in-system. Another name for FPDs is
  programmable logic devices (PLDs).

Source S. Brown and J. Rose, FPGA and CPLD
Architectures A Tutorial, IEEE
Design and Test of Computer, 1996
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Classifications

• PLA a Programmable Logic Array (PLA) is a
  relatively
• small FPD that contains two
  levels of logic, an AND-
• plane and an OR-plane, where
  both levels are
• programmable
• PAL a Programmable Array Logic (PAL) is a
  relatively
• small FPD that has a
  programmable AND-plane
• followed by a fixed OR-plane
• SPLD refers to any type of Simple PLD, usually
  either a
• PLA or PAL
• CPLD a more Complex PLD that consists of an
• arrangement of multiple
  SPLD-like blocks on a
• single chip.
• FPGA a Field-Programmable Gate Array is an
  FPD
• featuring a general structure
  that allows very high
• logic capacity.

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Programmable Logic Array (PLA)
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Programmable Logic Array (PLA)
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PAL
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PAL with Logic Expanders
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PLA v.s. PAL
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Complex PLD (CPLD)

• A CPLD comprises multiple PAL-like blocks on a
  single chip with programmable interconnect
  to connect the blocks.

• CPLD Architecture

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FPGA Overview

• Basic idea two-dimensional array of logic blocks
  and flip-flops with a means for the user to
  configure
• 1. the interconnection between the logic
  blocks,
• 2. the function of each block.

Simplified version of FPGA internal architecture
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FPGA
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FPGA

• Families of FPGAs differ in
• Physical means of implementing user
  programmability,
• arrangement of interconnection wires, and the
  basic functionality of the logic blocks.
• Most significant difference is in the method for
  providing flexible blocks and connections

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FPGA v.s. CPLD

• Capacitance

SPLDs CPLDs FPGAs
Equivalent gates 0 200 200 12,000 1000 1,000,000

• Applications

CPLDs
FPGAs

1. Implement random glue logics or Replace circuits
   previously implemented by multiple SPLDs
2. Circuits that can exploit wide AND/OR gates, and
   do not need a very large number of flip-flops
   are good candidates for implementation in CPLDs.

• FPGAs can be used in various applications
  prototyping, FPGA-based computers, on-site
  hardware re-configuration, DSP, logic emulation,
  network components, etc.

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Programming Technologies
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Programming Techniques in Configurable ICs
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Poly-Diffusion Antifuse
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Example Antifuse Techniques in PAL PLA
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Metal-Metal Antifuse
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SRAM-Based Programming technique
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Example SRAM-Controlled Programmable Switch
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EPROM EEPROM Programming technique
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EPROM EEPROM Programming technique

• Implementation of wired-AND gate

X
Y
X
X
Y
Y
High Vt
Low Vt
Low Vt
High Vt
X
X
Y
Y
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Comparison of Different Programming Techniques
Programming technology SRAM Poly-Diffusion antifuse Metal-Meta antifuse EPROM EEPROM
Manufacturing Complexity - - - -
Re-programmable? Yes In circuit No No Yes Out of circuit Yes In circuit
Physical size Large (12X) Small (2X) Small (1X) Small Small
ON resistance (?) 600800 100500 3080 1-4K 1-4K
OFF capacitance (fF) 1050 35 1 1050 1050
Power consumption - -
Volatile? Yes No No No No
Desirable - no desirable
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ASICs vs. FPLDs