Port Card Status

1
Port Card Status

• Paul Padley
• Mike Matveev
• Florida, August, 2000

2
Recall the last Review of PC

• It was a disaster
• In response, we split the responsibilities
• Ted Nussbaum became responsible for the schematic
• Nick Adams guided him to produce the schematic

3
JTAG
VME Interface Altera EPM9320GC280
VME
JTAG
From CCB
CCB Interface
From TMB1
DS90CR286 x3
Sorter, LUT, FIFO buffers Altera EPF10K200E 599-p
in PGA
GL
OPTICAL MODULE
GL
OPTICAL MODULE
GL
OPTICAL MODULE
From TMB2
DS90CR286 x3
To SR
GL
OPTICAL MODULE
GL
OPTICAL MODULE
From TMB3
DS90CR286 x3
GL
OPTICAL MODULE
Fig.1 Muon Port Card Block Diagram
4
Meanwhile

• Mike has worked in his spare time on a backup
  solution for the Port Card Logic
• We have implemented that solution and do not
  expect to pursue Nicks deisgn any further

5
SORTER
CHIP COMPRISES - Six LUT
RAM buffers 10248 bit each - Source
FIFO 240-bit wide and 8-bit deep for data
representing six input muons -
Sorter 3 best objects out of 18 -
Destination FIFO 120-bit wide and 8-bit deep
for data representing three best selected
muons - VME interface for all LUT RAM
and FIFO buffers - Circuitry for BX
synchronization checking STATISTICS
- 75 of logic cells used - 50
of embedded RAM used - 470 I/O pins
available, 420 used - 43 MHz registered
performance
6
MUON 1
DFF
TMB 1
PIPELINE MUON 1
DFF
MUX
MUX
10
8
LUT
FIFO_B MUON 1
VME
FIFO A
VME
VME
PIPELINE MUON 2
DFF
MUX
MUON 2
10
DFF
8
LUT
VME
FIFO A
FIFO_B MUON 2
VME
TMB 2
VME
MUON 3
DFF
TMB 3
FIFO_B MUON 3
VME
SORTING LOGIC 3 OUT OF 18
CLOCK
VME
Fig.2 Muon Port Card Sorter PLD Block
Diagram
7
TRIGGER LATENCY
(Points of measurement with scope on
existing prototypes shown ltlt) - TMB
logic (from LCT channel link receiver to MPC
link transmitter) ... 5 BX
125 ns ltlt - TMB channel link transmitter
to MPC channel link receiver (intrinsic
channel link chipset latency is
TTccd (2TRccd), where T is clock
period).... 2 BX 50 ns - MPC logic
Channel Link latency for
deserialization... 2 BX 50 ns ltlt
LUT conversion 1 BX
25 ns Sorting 3 out of
18 2 BX 50 ns
Output multiplexing 1 BX 25
ns Latching into G-link
transmitter 1 BX 25 ns ltlt
G-link latency for serialization
1 BX 25 ns - Optical cable, 100
m 21 BX 525 ns - SR logic
G-link latency for
deserialization 2 BX 50 ns ltlt

8
DONE by
August 25 1. Two boards were built, one
more will be assembled by mid September 2.
Sorter logic 3 out of 18 was simulated
separately and embedded into MPC
design with reduced latency (2BX vs 3BX) 3.
All VME functions were checked (LUT RAMs, FIFOs,
CSRs) 4. Test patterns were sent from source
FIFO and TMB and sorting logic was
checked with a limited number of LUT
combinations 5. Optical connection to SR
was checked 6. Latencies were measured in
several points of TMB-MPC-SR path 7. MPC
manual was prepared
9
FULL SIZE
MPC Design issues 1. Communication with 9
Trigger Motherboards - backplane or cables?
- parallel or serialized transmission?
- 40Mhz or 80Mhz? 2. Sorter implementation
- single chip logic requires 720 (630) inputs
120 outputs 840 (750) I/O 3. Optical
connection to Sector Processor crate -
serialization/deserialization inside FPGA or
outside? - single-channel or multi-channel
optical modules? - data rate (160Mbps ...
2.5Gbps)? 4. Radiation resistance (to SEU)
- periodical FPGA reloading from on-board PROMs
on TTC command? - functional redundancy
(double or triple internal circuitry)? -
Xilinx radiation hard FPGA family instead of
Altera? - common approach for all boards in
the peripheral crate 5. Integrate MPC logic and
peripheral CCB on a single board
10
Next Prototype

• Next prototype must come as close to final design
  as possible
• The PC is much more difficult than we had
  anticipated
• The next prototype will be a very complicated
  board, much more so than the current prototype