Noise in Sub 100nm Transistors and Nanostructures

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Noise in Sub 100nm Transistors and Nanostructures

• Investigation of 1/f noise in 100nm MOSFETs.
• Silicon nanopillars used as foundation for two
  vertical MOSFET devices
• Possible zero-trap device implemented using
  cylindrical surrounding-gate transistor.
• Carriers separated from oxide traps using
  depletion-mode surrounding-gate transistors.
• Time and frequency domain noise measurements
  planned.

Nanopillar core
62nm
500nm
Polysilicon gate
SEM picture after partial gate etch. Physical
gate length 500nm.
User Theresa Kramer, Stanford University Principa
l Investigator R.F.W. Pease, Stanford
University NNUN Site Stanford University