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Introduction to HDLs

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Introduction to HDLs. HDL (Hardware Description Language) VHDL versus Verilog ... How do IC designers use Verilog? Can be used for simulation ... – PowerPoint PPT presentation

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Title: Introduction to HDLs


1
Introduction to HDLs
  • HDL (Hardware Description Language)
  • VHDL versus Verilog
  • IC world only uses Verilog

2
How do IC designers use Verilog?
  • Can be used for simulation
  • Simulation at behavioral level, gate level, and
    at the switch level!
  • Can be used for circuit synthesis
  • Can be used to verify post-synthesis timing

3
Why Verilog and not VHDL?
  • C-like syntax (as opposed to Pascal-like!)
  • Better for circuit synthesis
  • I feel it is easier to create testbenches but
    others will dispute this claim!
  • Switch-level descriptions supported
  • Timing is more easily included
  • Can link in you own C-code!

4
Verilog Coding Styles
  • Behavioral Descriptions
  • Dataflow Descriptions
  • Gate-Level Descriptions (netlist)
  • Switch-Level Descriptions

5
Verilog Basics
  • Case-sensitive!!!!!
  • No special characters in variable names except _
  • Variable names must start with alpha character
  • Free-form
  • Very C-like

6
Concurrent Versus Sequential
  • Separate syntax to support descriptions of
    concurrent and sequential activity
  • Concurrent constructs best for describing
    combinational circuits
  • Sequential constructs must be used for describing
    sequential networks and for writing testbenches
    MAY be used for combinational circuits BUT BE
    CAREFUL!

7
First Example
// // First example // module first_example(f, x,
y, z) input x, y, z output f
assign f (x y z) (x y z)
(x y z) endmodule
8
First Example Testbench
// // Testbench for first example // timescale
1ns/100ps module first_example_tb reg
x, y, z wire f integer fid
first_example u0(f, x, y, z) initial
begin fid fopen("./first_example.out")
fmonitor(fid, time, " x b,
y b, z b, f b", x, y, z, f)
100 x 1'b0 y 1'b0 z 1'b0
100 x 1'b1 y 1'b1 z 1'b0
100 x 1'b1 y 1'b1 z 1'b1
100 finish end endmodule
9
Running Verilog XL
To simulate first example do the following
verilog first_example_tb.v first_example.v OR Cr
eate a file called, for example, modules and on
separate Lines place the two filenames from
above and give the Command verilog f modules
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