332:438 Capstone Design Digital Systems VLSI Track

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332438Capstone Design Digital SystemsVLSI
Track

• Instructor Prof. Michael L. Bushnell
• Teaching Assistant
• Course web site
• http//www.caip.rutgers.edu/bushnell
• ECE Department Rutgers University

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Changes in ECE Undergrad. Hardware Courses
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Capstone Design Course

• Second term of a 2-term sequence
• 1st term Academic content (as before)
• 2nd term Design Project (exclusively)
• Use automatic logic synthesis to synthesize
  project as logic gates, then do a chip layout for
  a System-on-a-Chip
• This course has
• No homework
• No examinations
• No Final Exam
• No academic lectures

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So What Are We Doing Here?

• A significant hardware design project
• Coded in Verilog
• Mapped by the Synopsys system into logic gates
  then you make a chip layout
• Team Size 5-6 people
• Projects must adhere to a strict schedule
• Bushnell functions as project team manager
• Weekly or bi-weekly design reviews 15 minute
  meeting nearly every week
• Accountability for all team members

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Project Deliverables
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Project Proposal

• Clear statement of what you will be designing
• System block diagram
• Statement of what system part each student will
  be designing
• Estimate of logic gates in each part
• Due 2/1/08, or you lose ½ letter grade

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Project Specification and System Block Diagram

• Statement of whether speed, cost,
  fault-tolerance, or low power consumption is most
  important (usually, some combination of the above
  is needed)
• Projected clocking rate
• Projected power consumption and power budget for
  each part (if power is important)
• Battery technology (if wireless portable device)
• Fault-tolerance strategy (if important)
• Hardware verification strategy
• Proposed testing strategy
• Social benefit of device being designed

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Project Specification and System Block Diagram

• Projected cost based on volume production
• Itemized parts list
• Electronic chip that you are designing
• Off-the shelf commercial chips
• Housing
• Power Supply
• Battery
• Keyboard
• Cables
• Due 2/8/08, or you lose ½ letter grade

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Example System Controller
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System Timing Diagram

• Due 2/15/08, or you lose ½ letter grade

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Example Flow Diagram
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Mnemonic Documented StateDiagram for Controller
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Controller Timing Diagram
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Detailed Economic Cost Analysis

• How do I do this?
• Information sources
• Web search
• Parts catalogs chip companies, battery
  manufacturers, housing makers, cabling makers
• Specifications from hardware companies for
  existing parts or systems that resemble yours
• Figure out everything in the design, find its
  cost, and add up all of the costs
• Due 2/22/08, or you lose ½ letter grade

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Chip Power Estimation Due

• Due 2/22/08

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Behavioral Verilog Code

• Due 2/29/08, or you lose ½ letter grade

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Behavioral Verilog Simulation

• Due 2/29/08, or you lose ½ letter grade

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Synthesized Verilog Logic

• To get this
• Read in behavioral design into design_analyzer
• Tell it to optimize the design hardware
• File-gtSave As command
• Change File format from .db to .v (verilog)
• Give it a unique file name for the structural
  verilog code
• Due 3/14/08, or you lose ½ letter grade

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Structural Verilog Example

• module adder ( addend, augend, sum, carry_in,
  agenerate,
• propagate,
• carry_in_LSB,
  carry_out_MSB )
• input 02 addend
• input 02 augend
• output 02 sum
• inout 02 carry_in
• inout 02 agenerate
• inout 02 propagate
• input carry_in_LSB
• output carry_out_MSB

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Example (continued)

• wire n16, n17, n18, n19, n20, n21
• tri carry_in_LSB
• tri \carry_in1
• tri \carry_in2
• tri 02 agenerate
• tri 02 propagate
• tran( carry_in_LSB, carry_in0)

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Example (concluded)

• NAND2C U28 ( .A(addend0), .B(augend0),
  .Out(agenerate0) )
• NAND2C U29 ( .A(addend1), .B(augend1),
  .Out(agenerate1) )
• NAND2C U30 ( .A(addend2), .B(augend2),
  .Out(agenerate2) )
• NAND2 U31 ( .A(n16), .B(n17), .Out(carry_in1)
  )
• INV U32 ( .A(agenerate0), .Out(n17) )
• NAND2 U33 ( .A(carry_in_LSB), .B(propagate0),
  .Out(n16) )
• NAND2 U34 ( .A(n18), .B(n19), .Out(carry_in2)
  )
• INV U35 ( .A(agenerate1), .Out(n19) )
• NAND2 U36 ( .A(propagate1), .B(carry_in1),
  .Out(n18) )
• XOR2 U37 ( .A(augend0), .B(addend0),
  .Out(propagate0) )
• XOR2 U38 ( .A(augend1), .B(addend1),
  .Out(propagate1) )
• XOR2 U39 ( .A(augend2), .B(addend2),
  .Out(propagate2) )
• XOR2 U40 ( .A(carry_in2), .B(propagate2),
  .Out(sum2) )
• XOR2 U41 ( .A(carry_in1), .B(propagate1),
  .Out(sum1) )
• XOR2 U42 ( .A(propagate0), .B(carry_in_LSB),
  .Out(sum0) )
• NAND2 U43 ( .A(n20), .B(n21),
  .Out(carry_out_MSB) )
• INV U44 ( .A(agenerate2), .Out(n21) )
• NAND2 U45 ( .A(carry_in2), .B(propagate2),
  .Out(n20) )
• endmodule

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Verilog Logic Simulation

• Simulates the structural verilog code to see if
  it is correct
• Takes a lot longer than behavioral simulation
• Requires you to insert module definitions in
  front of your code (I will supply these)
• Ensures that automatic logic synthesis did not
  incorrectly generate the logic
• Use the same testbench as for behavioral
  simulation
• Due 3/14/08, or you lose ½ letter grade

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Testing Method Hardware

• For each module in design, you need one of these
• Test patterns generated by Rutgers spectral ATPG
  (automatic test-pattern generator)
• Built-In Self-Testing Hardware for Random Logic
  using the BILBO
• Built-In Self-Testing Hardware for Memory
• For the entire design, you need
• JTAG Boundary Scan Hardware to break it into
  parts that can be separately tested
• Testing plan for the interconnect between the
  parts
• Due 3/21/08, or you lose ½ letter grade

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Chip Slice Plan

• Due 3/14/08

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Chip Floor Plan

• Due 3/14/08

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Chip Leaf Cells

• Due 4/18/08

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Tiny Chip Project

• Some portion of your SoC Project
• Implemented on an AMIS 0.6 micron fab. Line
• We will actually make and test these chips
• Should be a small sub-assembly of your
  System-on-a-Chip Project
• Limit 35 pads
• Due 4/18/08

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Testing Fault Coverage and Test Patterns

• For combinational circuits
• For sequential circuits
• Due 4/25/08, or you lose ½ letter grade

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Routed Chip Layout

• Due 4/25/08

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Public Safety and Environmental Impact Statement

• Answer these conditions
• Is this device dangerous?
• If so, under what conditions?
• What precautions need to be taken with your
  device?
• Does this device affect the environment?
• Chemically, Electrically, Optically, or
  Otherwise?
• How can the user avoid these problems?
• Due 4/25/08, or you lose ½ letter grade

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Routed Chip Timing Analysis

• Includes Extracted Circuit Simulations
• Due 4/25/08

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Final Project Presentation

• Requirements
• Done in Powerpoint
• Presented to the entire class and ECE Dept.
  Faculty
• Addresses each one of the deliverables (in
  summarized form)
• Do not attempt to show the entire hardware show
  only block diagram or 1 or 2 more interested
  hardware modules
• Due 5/2/08, or you lose ½ letter grade

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Final Project Report

• Data book description of part
• Voluminous but clear description of everything
• Needs to be organized with a Table of Contents
• Needs to be grammatically correct with no
  spelling errors
• Needs to be bound into a single document
• Due 5/2/08, or you lose ½ letter grade

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Confusion Between Verification and Testing

• Verification
• Done once in lifetime of design
• Consists of verilog behavioral and logic
  simulations with testbench
• Proves that there are no logic errors (bugs) in
  the design
• Testing
• Done forever as long as the design is in
  production
• Each chip made from the design is tested
• Chips are quizzed by Automatic Test Equipment
  (grader) with test patterns (examination) and
  responses (student answers) are graded (checked
  for correctness)