Mixing HandelC with VHDL

1
Mixing Handel-C with VHDL
2
VHDL in Handel-C (1)

• ENTITY parmult IS
• port (
• clk IN std_logic
• a IN std_logic_VECTOR(7 downto 0)
• b IN std_logic_VECTOR(7 downto 0)
• q OUT std_logic_VECTOR(15 downto 0))
• END parmult
• interface parmult (unsigned 16 q)
  parmult_instance (unsigned 1 clk, unsigned 8 a,
  unsigned 2 b) with busformat "B(I)"

3
VHDL in Handel-C (2)

• unsigned 8 x1, x2
• unsigned resultX
• interface parmult
• (unsigned 16 q)
• parmult_instance1
• (unsigned 1 clk __clock,
• unsigned 8 a x1,
• unsigned 8 b x2 )
• with busformat "B(I)"

4
VHDL in Handel-C (3)

• while (1)
• par
• x1 some_value
• x2 some_value
• resultX parmult_instance1.q

5
Handel-C in VHDL (1)

• component handelc_component
• port (
• clk in std_logic
• sent_value in unsigned (3 downto 0)
• return_val out unsigned (3 downto 0)
• )
• end component

6
Handel-C in VHDL (2)

• unsigned 4 x
• interface port_in (unsigned 1 clk with
  clockport1) ClockPort ()
• interface port_in (unsigned 4 sent_value)
  InPort ()
• interface port_out () OutPort (unsigned 4
  return_value x)
• set clock internal ClockPort.clk
• void main(void)
• unsigned 4 y
• y InPort.sent_value // Read from
  top-level VHDL
• x y // Write to
  top-level VHDL