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Title: Lecture 12 Introduction to VHDL


1
Lecture 12Introduction to VHDL
  • Hai Zhou
  • ECE 303
  • Advanced Digital Design
  • Spring 2002

2
Outline
  • VHDL Language Basics
  • Interface
  • Architecture Body
  • Process
  • Signal Assignment and Delay Models
  • Various Sequential Statements
  • READING Dewey 11.2, 11.3, 11.4, 11.5. 11.6,
    15.1, 15.2, 18.2, 18.3, 18.4, 18.5

3
Modeling Digital Systems
  • Digital system Any digital circuit that
    processes or stores information in digital form
    gates to functional units
  • Model represents only relevant information and
    abstracts away irrelevant detail
  • Model needed to
  • Develop and specify requirements
  • Communicate understanding of a system to a user
  • Allow testing of design through simulation
  • Allow formal verification
  • Allow automated synthesis

4
What is VHDL
  • (Very High Speed Integrated Circuits) VHSIC
    Hardware Description Language
  • Used for two things
  • (1) Used to model digital systems, designs can
    then be SIMULATED
  • A simulator runs a VHDL description computing the
    outputs of a modeled system
  • (2) Used as a language to enter designs into CAD
    tools, designs can then be SYNTHESIZED
  • VHDL also provides a blackboard for designing
    digital systems
  • An initial design is progressively expanded and
    refined
  • Another popular hardware language is Verilog

5
Relationship between VHDL and hardware
VHDL description
Simulator
Hardware
Simulated / actual outputs
Model
6
Example of VHDL Description
VHDL Model of a 2input exclusive OR gate
entity XOR2_OP is -- input output ports port
(A, B in BIT Z out BIT) --
Body architecture EX_DISJUNCTION of XOR_OP2
is begin Z lt A xor B end EX_DISJUNCTION

7
VHDL Entity Definitions
  • A VHDL entity consists of two parts
  • interface denoted by keyword entity
  • body denoted by keyword architecture
  • Interface describes aspects visible outside
  • Body describes how black box operates inside
  • FORMAT
  • entity identifier is
  • port (name in / out / inout BIT/type)
  • end identifier
  • -- lines beginning with two dashes are
    comments

8
VHDL Architecture Body
  • Architecture body describes how entity operates
  • Allows for different implementations
  • Can have behavioral or structural or mixed
    representations
  • FORMAT
  • architecture EX_DISJUNCTION of XOR_OP2 is
  • begin
  • Z lt A xor B
  • end EX_DISJUNCTION

9
Architecture Body
  • Body is divided into two parts
  • Declarative part
  • Statement part
  • architecture EX_DISJUNTION of XOR_OP2 is
  • -- declarative part
  • -- objects must be declared before they are used
  • begin
  • -- statement part
  • Z lt A xor B
  • end EX_DISJUNCTION

10
Data Types in VHDL
  • The type of a data object defines the set of
    values that object can assume and set of
    operations on those values
  • VHDL is a strongly typed language
  • Four classes of objects
  • constants
  • variables
  • signals
  • files

11
Constant Declaration
  • The value of a constant cannot be changed
  • FORMAT
  • constant identifier , subtype
    expression
  • EXAMPLES
  • constant number_of_bytes integer 4
  • constant prop_delay time 3nsec
  • constant e real 2.2172

12
Variable Declaration
  • The value of a variable can be changed
  • FORMAT
  • variable identifier , .. subtype
    expression
  • EXAMPLES
  • variable index integer 0
  • variable sum, average, largest real
  • variable start, finish time 0 nsec

13
Variable Assignment Statement
  • Once a variable is declared, its value can be
    modified by an assignment statement
  • FORMAT
  • label name expression
  • EXAMPLES
  • program_counter 0
  • index index 1
  • Variable assignment different from signal
    assignment
  • A variable assignment immediately overviews
    variable with new value
  • A signal assignment schedules new value at later
    time

14
Scalar Types
  • Variable can only assign values of nominated type
  • Default types
  • integer , real, character, boolean, bit
  • User defined types
  • FORMAT
  • type small_int is range 0 to 255
  • Enumerated type
  • FORMAT
  • type logiclevel is (unknown, low, driven,
    high)

15
Sub Types
  • A type defines a set of values
  • We can define a sub-type as a restricted set of
    values from a base type
  • FORMAT
  • subtype identifier is name range
    simple_expression to/downto simple_expression
  • EXAMPLE
  • subtype small_int is integer range -128 to 127
  • subtype bit_index is integer range 31 downto 0

16
Attributes of Types
  • A type defines a set of values and set of
    applicable operations
  • A predefined set of attributes are used to give
    information about the values included in the type
  • Tleft first (leftmost) value in T
  • Tright last (righmost) value in T
  • Tvalue(s) the value in T that is represented
    by s
  • EXAMPLES
  • type set_index_range is range 21 downto 11
  • set_index_rangeleft 21
  • set_index_rangeright 11
  • set_index_rangevalue(20) 20

17
Expressions and Operators
18
VHDL Modeling Concepts
  • Semantics (meaning) is heavily based on
    SIMULATION
  • A design is described as a set of interconnected
    modules
  • A module could be another design (component) or
    could be described as a sequential program
    (process)

19
A general VHDL design
Entity is End entity
I1
O1
I2
IO1
s1
component
concurrent assignment
I1
O1
s2
architecture of is ... begin end
s3
s4
s8
s9
s6
process 1
process 2
concurrent assignment
I2
IO1
s5
s7
20
VHDL Simulator
start
Init t 0
more event
stop
get earliest event
delta delay
advance time
update signals
execute triggered processes
during process execution, new events may be added
21
Process Statements
  • FORMAT
  • PROCESS_LABEL process
  • -- declarative part declares functions,
    procedures, types, constants, variables, etc
  • begin
  • -- Statement part
  • sequential statement
  • sequential statement
  • wait statement -- eg. Wait for 1 ms or wait on
    ALARM_A
  • sequential statement
  • wait statement
  • end process

Flow of control
22
Sequential Statements
  • Sequential statements of various types are
    executed in sequence within each VHDL process
  • Variable statement
  • variable expression
  • Signal Assignment
  • If statement
  • Case statement
  • Loop statement
  • Wait statement

23
Variable and Sequential Signal Assignment
  • Variable assignment
  • new values take effect immediately after
    execution
  • variable LOGIC_A, LOGIC_B BIT
  • LOGIC_A 1
  • LOGIC_B LOGIC_A
  • Signal assignment
  • new values take effect after some delay (delta if
    not specified)
  • signal LOGIC_A BIT
  • LOGIC_A lt 0
  • LOGIC_A lt 0 after 1 sec
  • LOGIC_A lt 0 after 1 sec, 1 after 3.5 sec

24
Signal Declaration and Assignment
  • Signal declaration describes internal signal
  • signal identifier subtype
    expression
  • EXAMPLE
  • signal and_a, and_b bit
  • Signal Assignment
  • name lt value_expression after
    time_expression
  • EXAMPLE
  • y lt not or_a_b after 5 ns
  • This specifies that signal y is to take on a new
    value at a time 5 ns later statement execution.
  • Difference from variable assignment
  • which only assigns some values to a variable

25
Concepts of Delays and Timing
  • The time dimension in the signal assignment
    refers to simulation time in a discrete event
    simulation
  • There is a simulation time clock
  • When a signal assignment is executed, the delay
    specified is added to current simulation time to
    determine when new value is applied to signal
  • Schedules a transaction for the signal at that
    time

output
input
26
Specifying Technology Information
  • One predefined physical type in VHDL TIME
  • Units fs (10 -15 seconds), ps (1000 fs), ns,
    us, ms, sec, min ( 60 sec), hr (60 min)
  • User-defined physical types
  • type CAPACITANCE is range 0 to INTEGERHIGH
  • units
  • fF -- Femtofarads
  • pF 1000 fF -- Picofarads
  • nF 1000 pF -- Nanofarads
  • end units
  • type VOLTAGE is range 0 to 2 32 -1
  • units
  • uV -- Microvolt
  • mV 1000 uV
  • V 1000 mV
  • end units

27
Specifying Delays
  • Inertial Delay Model
  • reflects physical inertia of physical systems
  • glitches of very small duration not reflected in
    outputs
  • SIG_OUT lt not SIG_IN after 7 nsec --implicit
  • SIG_OUT lt inertial ( not SIG_IN after 7 nsec )
  • Logic gates exhibit lowpass filtering

3 ns
10ns
SIG_IN
2ns
SIG_OUT
9 ns
19 ns
28
Transport Delays
  • Under this model, ALL input signal changes are
    reflected at the output
  • SIG_OUT lt transport not SIG_IN after 7 ns

3 ns
10ns
SIG_IN
2ns
SIG_OUT
9 ns
19 ns
30 ns
29
If Statement
  • FORMAT
  • if boolean_expression then
  • sequential statement
  • elsif boolean_expression then
  • sequential statement
  • else sequential statement
  • endif
  • EXAMPLE
  • if sel0 then
  • result lt input_0 -- executed if sel 0
  • else result lt input_1 -- executed if sel
    1
  • endif

30
Case Statement
  • EXAMPLE of an ALU operation
  • case func is
  • when pass1 gt
  • result operand1
  • when pass2 gt
  • result operand2
  • when add gt
  • result operand1 operand2
  • when subtract gt
  • result operand1 - operand2
  • end case

31
Loop Statements
  • While condition loop
  • sequential statements
  • end loop
  • for identifier in range loop
  • sequential statements
  • end loop
  • while index gt 0 loop
  • index index -1
  • end loop
  • for count in 0 to 127 loop
  • count_out lt count
  • wait for 5 ns
  • end loop
  • for i in 1 to 10 loop
  • count count 1
  • end loop

32
Wait Statement
  • A wait statement specifies how a process responds
    to changes in signal values.
  • wait on signal_name
  • wait until boolean_expression
  • wait for time_expression
  • Example on right shows process sensitivity list
  • EXAMPLE SAME AS

half_add process is begin sum lt a xor b
after T_pd carry lt a and b after T_pd
wait on a, b end process
half_add process (a,b) is begin sum lt a
xor b after T_pd carry lt a and b after
T_pd end process
33
Example of Architecture Body(AND_OR_INVERT)
or_gate process (and_a, and_b) is begin
or_a_b lt and_a or and_b end process
or_gate inv process (or_a_b) is begin y
lt not or_a_b end process inv end architecture
primitive
architecture primitive of and_or_inv is signal
and_a, and_b, or_a_b bit begin and_gate_a
process (a1,a2) is begin and_a lt a1 and
a2 end process and_gate_a and_gate_b process
(b1,b2) is begin and_b lt b1 and b2 end
process and_gate_b
a1 a2
y
b1 b2
34
Process Declaration of Clock Generator
Clock_gen process (clk) is begin if clk
0 then clk lt 1 after T_pw, 0
after 2T_pw endif end process clock_gen
2T_pw
T_pw
35
Process Generator for Multiplexer
mux process (a, b, sel) is begin case sel
is when 0 gt z lt a after
prop_delay when 1 gt z lt b
after prop_delay end process mux
a
z
b
sel
36
Summary
  • VHDL Language Basics
  • Interface
  • Architecture Body
  • Process
  • Signal Assignment and Delay Models
  • Various Sequential Statements
  • NEXT LECTURE VHDL Structural Description
  • READING Dewey 12.1, 12.2, 12.3, 12.4, 13.1,
    13.2, 13.3. 13.4, 13.6, 13.7. 13.8
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