Diapositiva 1

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Comparing VHDL and VHDL-AMS for Modelling and
Simulation of Power Converters with Digital
Control
A. de Castro, T. Riesgo, O. García, R.
Prieto Universidad Politécnica de Madrid División
de Ingeniería Electrónica www.upmdie.upm.es
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Main goal
Validate digital controllers for power converters

Particular case controllers described in VHDL
Few mixed (analog/digital) simulators
VHDL or VHDL-AMS models for analog parts
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Outline

• Introduction
• Digital control for power converters
• Custom hardware implementations
• Simulation Options
• Mixed-signal simulators
• VHDL or VHDL-AMS models
• VHDL Models
• VHDL-AMS Models
• Comparison
• Conclusions and future work

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Introduction
Power converters

• Complex control algorithms
• Components count
• Design time

• Price
• ADCs needed

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Introduction
Increase of digital controllers for power
converters
Becoming a hot-topic
Most solutions are DSP-based
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Introduction
Custom Hardware
VHDL
TheCounter process(Clk, ResN) begin if ResN
'0' then Counter lt 0 elsif Clk '1' and
Clk'event then if Counter lt (NCycles-1) then
Counter lt Counter 1 else
Counter lt 0 end if end if end process
TheCounter
In order to validate the controller SIMULATION is
required
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Complete simulation scheme
Closed-loop as the best way to validate the
controller
Control Signals (for the switches)
Digital
Analog
Measured State Variables (real type)
Measured Variables (digital buses)
Mixed
How to simulate the complete system?
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Mixed-Signal Simulators
Digital Controller
Matlab/Simulink
Transfer function

• Not very precise
• Two models of the controller are needed

PSIM
Transfer function or C/C code
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VHDL or VHDL-AMS Simulators
Switching Power Converter
A/D Converter
Same controller description for both simulation
and synthesis
Simple power converter and ADC models (goal
controller validation)
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Power Converter VHDL Model

• Obtaining the differential equations for each
  circuit state (depending on the switches)
• Translating the differential equations to finite
  difference equations
• Coding the finite difference equations in VHDL

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Power Converter VHDL Model
entity FlybackModel is port( Vin in
real Rl in real Ir
in real Resist in boolean
OnOff in std_logic ResN in
std_logic Iin out real Il1
out real Vout out real ) end
FlybackModel
Non-synthesizable VHDL

• Most variables in real type
• Event-driven simulation converted to time-driven
  simulation (wait for)

• Only ideal components
• Fixed time-step (?t)
• Explicit finite difference equations (simpler
  algorithms)

Simple model ? fast simulation
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Power Converter VHDL-AMS Model
Model creation through schematics
No finite difference equation (the simulator
deals with this)
Most components defined in libraries
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VHDL and VHDL-AMS Models
VHDL
VHDL-AMS
i cap v'dot
v ind i'dot
if OnOff '1' then -- closed switch Il1Aux lt
Il1Aux ( (Uedt) / L1 ) UsAux lt UsAux - (
(Irdt) / C ) else -- open switch Il1Aux lt
Il1Aux - ( (UsAuxdt) / (nL1) ) UsAux lt
UsAux ( ( ( (Il1Aux/n) - Ir ) dt ) / C ) end
if wait for Cycle
L1 entity work.inductor(ideal) generic
map( ind gt 352.4e-6 ) port
map( p1 gt XSIG010010, p2
gt ELECTRICAL_REF ) C1 entity
work.capacitor(ideal) generic map(
cap gt 345.4e-6 ) port map(
p1 gt ELECTRICAL_REF, p2 gt
XSIG010002 )
Finite difference equations
Differential equations and components connection
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A/D Converter VHDL or VHDL-AMS Model
Digital output (std_logic_vector)
Analog input (real type)
A/D Converter
Control signals

• Format conversion (real to std_logic_vector)
• Conversion delays considered
• Conversion on demand (answering to the control
  signals)

Almost the same model using VHDL or VHDL-AMS
SAR (Successive Approximation Register) technique
employed
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VHDL vs VHDL-AMS Comparison
Flyback converter working as Power Factor
Corrector (PFC)
VHDL
Input current
Output voltage
VHDL-AMS
Models validation through experimental results
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VHDL vs VHDL-AMS Comparison
VHDL
VHDL-AMS
Control over the model (changing the time-step or
results file size)
Easy model creation (schematics and no finite
difference equations)
Available tools (VHDL std in 1987, VHDL-AMS std
in 1999)
Results visualization (analog waveforms displayed
by the simulator)
Simulation time
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Conclusions and future work

• VHDL and VHDL-AMS models for power converters
• Goal digital controller validation
• Controller developed in VHDL ? VHDL or VHDL-AMS
  models for the power converter and A/D converter
• Simple ideal models ? enough for the controller
  validation and fast simulation
• VHDL models are faster and more flexible
• VHDL-AMS models are easier to create
• Future work
• Library of power converters models (different
  topologies, already done in VHDL-AMS)