IBM / Cadence

1
IBM / Cadence

• Tom Bartenstein
• TestBench Architect

2
STIL Application Overview

• Integration and support plan
• IBM read STIL for Mfg. Test data
• TestBench
• Write STIL for ATPG patterns
• Read STIL for fault sim, test data migration,
  etc.
• Flow/methodology
• IBM STIL import for Mfg. Test
• TestBench
• STIL output to Mfg.
• STIL input for fault grading external patterns,
  etc.
• STIL input for core test methodology

3
Current Status IBM

• Progress report
• Verified STIL tools by correlating dual path for
  patterns
• Acquired patterns in both STIL WGL format
• Processed STIL through new internal tools
• Processed WGL through legacy tools
• Correlated results
• Integrated 3rd party tools with internal tools
  for more robust OEM pattern support
• Successes
• Processed STIL patterns for customer devices to
  various internal tester platforms
• MCC Burn-in tools
• Teradyne testers
• Advantest testers (underway)

4
Current Status IBM

• Technical issues
• Need to push OEM customers towards STIL as THE
  single pattern format
• Customers seem to be somewhat resistant
• STIL Complexity Issues
• Performance concerns relative to legacy tools
• Spec is somewhat daunting to potential new users
• Must strive for simplicity in follow-on 1450.X
  extensions
• Need to clarify ambiguities in the 1450.0 spec
• Each STIL Writer produces new flavors (TB,
  SourceIII, Synopsis, )
• Drives continual effort for STIL Readers
• Feedback spec issues for resolution into the 1450
  clarification docs

5
Current Status TestBench

• Progress report
• STIL writer delivered 2001
• Verification through IBM STIL reader
• STIL reader delivered 2002
• Verification through customer STIL examples and
  round trip, including re-simulation
• Successes
• Minimal customer use

6
Current Status TestBench

• Technical Issues
• Scan Protocols
• Encapsulated in scan macro, or expanded into
  patterns?
• Multiple protocols in a single pattern set?
• Complexity
• Too many ways to do the same thing
• Forces continual updates for readers

7
Benefits

• Flow
• Reduced development for multiplicity of pattern
  formats (WGL, VCD, )
• More focused support
• Simplified support
• Enabler for pattern transfer
• Core -gt chip
• Functional fault grading
• Etc.
• QOR
• Too soon to tell

8
Future Plans

• IBM Continued groom of internal tools to
  support STIL 1450.0 for MFG test
• Add capability as needed
• Do not support entire 1450.0 spec (I.e. cyclized
  patterns only)
• TestBench
• Improve scan protocol handling
• Integral part of SOC/core test methodology
• P1500/CTL follow-on work