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Delay Test with Integrated Timing Analysis

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The material originally was prepared for a Cadence Design Systems ... Source: Pat Gelsinger, Intel, ITC 1999. Added. resistance. Wiring is more significant in ... – PowerPoint PPT presentation

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Title: Delay Test with Integrated Timing Analysis


1
Delay Testwith Integrated Timing Analysis
2
Acknowledgement
  • The material originally was prepared for a
    Cadence Design Systems Webinar in 2004

3
Technology Issues
Wiring is more significant inNanometer designs
Addedresistance
Source Phil Nigh, ITC2001
4
Effect on Test/Stress Methods
Source Phil Nigh, ITC2001
5
Agenda
  • Scan-Based Delay Test
  • Methodology Considerations
  • Delay Test Overview
  • Defect Types
  • Product/Pattern Timing Considerations
  • Advanced Pattern Timing Capabilities
  • Wrap-up Discussion

6
IDDq Testing
  • IDDq testing detects defects that cause
    abnormally high quiescent power supply current
  • Devices that pass all other tests, but have
    abnormally high IDDq, have been found to be less
    reliable
  • Small number of IDDq patterns generally
    sufficient
  • Set up circuit state, wait for circuit to settle,
    measure current
  • Future of IDDq challenged by increasing
    background currents
  • Loss of signal-to-noise ratio
  • Increasing use of differential methods like
    Delta IDDq and/or Nearest Neighbor Residuals
    (NNR)

7
Very Low Voltage (VLV) Testing
  • VLV can amplify certain defects
  • E.g. defective delays increase more than normal
    delays
  • Achievable voltage level depends on
    process/design
  • Typically used with gross delay testing (30 or
    50 of target speed)
  • Minimal VDD (MinVDD)
  • Determine minimal voltage at which a test suite
    passes
  • Generally used together with other measurements
  • E.g., IDDq, maximum frequency (Fmax), ring
    oscillator frequency, etc.
  • All performance/process indicators should
    correlate any miscorrelation indicates potential
    defect or reliability problems

8
Advanced Flow with Post-Processing
Acknowledgement from a presentation by Bob
Madge, LSI Logic
9
Delay Defects The Issue
  • Signal transitions are delayed
  • errors persist only for limited time
  • may escape detection in test if strobed too late
    (DC test)

logic
FF
FF
Y
X
Clock
Clock
systemcycle
test strobe
X
systemfails
testpasses
Y
defect
Clock
10
Delay Defects What to Do
  • Tighten test timing
  • Move strobe as close to product limits as
    reasonably possible
  • Scan-Based delay test pattern options
  • twist modify DC tests (e.g. merge last scan Clk,
    PI Stims, capture clk into timed test cycle)
  • transition fault test transition fault model
    with ATPG, fault simulation, test timings
  • path delay ATPG for selected path(s)

systemcycle
testfails
test strobe
X
Y
defect
Clock
11
Delay Fault Models
  • Transition faults
  • Each gate input and output can be slow-to-rise or
    slow-to-fall
  • Conditional, temporary stuck-at faults
  • Assumption defective delay is long enough to be
    detected at given strobe timings (model itself
    includes no timing)

12
More Delay Fault Models
  • Path delay faults
  • Timed edge propagation along specific signal
    path(s)
  • Typically applied to small subset of all possible
    paths
  • Useful for characterization, process window,
    speed binning (paths with representative
    cross-section of function elements)
  • Not generally useful for random defects (too many
    paths)
  • Small delay faults
  • Include timing information and fault size
    (defective delay adder) of detectable delay
    faults
  • Mostly useful for calibrating delay test
    generation effectiveness

13
Scan-Based Delay Test Format
  • Modern delay test tools generate, time, and fault
    grade transition fault tests
  • generalized delay test format with explicit
    release
  • Note ONLY the dynamic events need to be at-speed
    timed for effective delay test
  • At-speed scan may be used, but is NOT required

static
dynamic
static
scan
init
rel.
prop.
capt.
copy
scan
stuck-at faults
delay faults
14
Simple Test Sequence
  • Utilizes scan data for transition creation
  • Release edge updates FF1 with data from scan side
    of mux
  • Capture edge strobes data at system side of FF2
  • Scan Enable must change between release and
    capture
  • BUT dynamic event timing is independent of scan
    timings

SE
Scan Data
0
0
1
1
System Data
Combinational
FF1
FF2
Logic
Clk
Scan
Scan
Dynamic Events
Copy
Clk
SE
Capture
Release
Propagate
15
Alternate Sequence
  • Characteristics of example
  • Release edge updates FF1 with data from system
    side of mux
  • Capture edge strobes data at system side of FF2
  • SE no longer critical for timing, BUT requires
    sequential test generation/simulation

SE
Scan Data
0
0
1
1
System Data
Combinational
FF1
FF2
Logic
Clk
Scan
Scan
Dynamic Events
Copy
Init
Clk
SE
Capture
Release
16
Delay Defects
  • Defects interact with process-induced statistical
    variations

17
Large Delay Defect Example
Defect Type 4 - CoSi2 Open
CoSi2
CoSi2
CMOS 6X tech, CP chip
CMOS 6X tech, CP chip
Open
Open
Detected by AC scan
Detected by AC scan
pattern
pattern
T0 fail
T0 fail
Defect size
100 ns on LSSD
Defect size
100 ns on LSSD
Latch
Latch
Diagnosed on Tester
Diagnosed on Tester
Source S/390 AC Defects and Experience, Peilin
Song, IBM ITC99
18
Small Delay Defect Example
Defect Type 1 - NFET Silicon Contamination

CMOS 5X tech, CP chip
Detected by
LBIST_OPCG pattern
Reliability fail
Defect size
125 ps

only on one transition
Diagnosed using both
TestBench and Tester
Source S/390 AC Defects and Experience, Peilin
Song, IBM ITC99
19
Experimental Defect Size Distributions
Source Chao-Wen Tseng, Stanford CRC, 2003
20
Sensitivity to Test Conditions
21
At-Speed Test Versus Static Test
  • For static testing, clocks can be always be
    slowed down to avoid setup-time problems
  • No setup-time constraints for test mode, test
    control signals
  • Greatly simplifies DFT insertion
  • BUT, hold-time constraints remain for
    edge-triggered scan
  • At-speed test adds setup-time constraints
  • Design now must meet two-sided constraints
    (hold-time AND setup-time) in test mode
  • Can create significant new timing closure
    problems
  • May affect test control signals as well as
    functional signals
  • Test modes generally are not identical to
    functional modes
  • Different clock sources, different signal paths
  • Can limit pattern timing due to mismatch between
    test clocks and functional clocking

Image source LogicVision
22
Test Clocks versus Functional Clocks
  • Test timing dominated by worst case path
    associated with each test clock domain

Domain A
Maintenance/multi-cycle Path
Domain B
SharedTest Clock
23
False Paths
0/1/1
0/1/1
5/5/0
1/0/-1
G3
G1
0/-2/-2
G5
lt2gt
3/1/-2
G2
5/3/-2
7/5/-2
lt1gt
lt2gt
lt2gt
0/-1/-1
3/3/0
1/1/0
G4
3/5/2
0/1/1
lt2gt
0/-1/-1
24
False Path Identification?
1!
G3
G1
G5
lt2gt
G2
lt1gt
lt2gt
lt2gt
1!
1!
conflict!
0gt
G4
lt1
1gt
lt2gt
1!
1!
G3
G1
G5
lt2gt
G2
lt1gt
lt2gt
lt0
lt2gt
1!
1gt
conflict!
0gt
G4
lt2gt
25
Be Careful.
a
f
f
d
G3
G1
b
e
G5
lt2gt
G2
h
lt1gt
lt2gt
lt2gt
g
G4
g
lt2gt
c
0
1
2
3
4
5
6
7
a
b
c
d
e
f
g
h
26
Path Slack Distribution
  • Design-induced variations across multiple paths

27
Propagation Path Considerations 1
  • Issue small defect may escape if tested on
    shorter path

Expected Arrival Time 1.57ns
Source S/390 AC Defects and Experience,Peilin
Song, IBM ITC99
delay defect (.36ns)
long path
Strobe at 1.6ns
Propagationpath
Defect persists Only to 1.29ns DefectEscapes!
short path
Expected Arrival Time .93ns (1.29ns with defect)
Note designed to work at 1.6ns
28
Constrained Timings in Encounter Test
  • Solution permit moving strobe in for tighter
    test
  • Integrated timing utility automatically corrects
    expect values

Expected Arrival Time 1.57ns
Fails Set-upMasked inCompare!
delay defect (.36ns)
long path
Strobemoved in to 1.0ns
Propagationpath
Meets Set-up DefectDetected!
short path
Expected Arrival Time .93ns
29
Propagation Path Considerations 2
  • Issue tighter strobe would fail set-up at
    capture latch
  • Capture latch would be masked in constrained
    timing

slack.67ns
.36ns delaydefect
short path
DefectEscapes!
long path
Strobe at 1.6ns
slack.03ns
30
AC/DC Lineholds in Encounter Test
  • Solution block or avoid transitions in longer
    path
  • Enforced by delay test ATPG
  • Integrated timing utility automatically accounts
    for lineholds

slack.67ns
.36ns delaydefect
short path
No transition(AC Linehold)
long path
DefectDetected!
Strobemoved in to 1.0ns
Hold at 0(DC Linehold)
slack.03ns
31
Product/Tester Interaction
  • Tester resolution, accuracy, pulse-width, and
    edge placement characteristics impact actual
    timings
  • Encounter Test can import and account for tester
    timing characteristics (Tester Description Rule,
    TDR)

32
On-Product Clock Generation
  • Move timing generators and control on-chip
  • intended for at-speed test and/or
    characterization
  • Note if designed right, it can be used with ATPG
    or BIST
  • E.g., utilize on-chip PLL for frequency/phase
    alignment

Reference Clock
Sample Clock Tree
Timing Generator (PLL- based or other)
Test Controller
. . .
Controls/ Test Clock
On-chip waveforms
Clock Test Out
33
Recent Scan Issues
  • Scan tests generate up to 10x of normal circuit
    activity
  • Concern for average power (power-supply limits,
    thermal)
  • Slower scan
  • Concern for switching noise (di/dt power supply
    response, inductive coupling to power supplies)
  • Reduction of transitions, Skewing of clock edges
    during scan, Partitioned scan, release, capture
  • Simultaneous I/O switching
  • Di/dt caused by simultaneously enabling/disabling/
    switching I/O drivers
  • Limited simultaneous driver switching
  • Scan test data volume and test times
  • Adjust scan I/O data bandwidth to maximize ATE
    utilization
  • ATE-based or on-chip data compression techniques

34
Diagnostics
  • Fast test problem debug
  • structural test methodology enables debug without
    having to know the function
  • Very useful for third-party IP and
    manufacturing/test outsourcing
  • Minimizes dependency on expert support from
    dis-integrated IP/tools/design/manufacturing/test
    supply-chain
  • automated logic diagnostics supported by full
    scan
  • memory diagnostics supported by bitmapping data
    interface
  • Must be able to collect detailed bit-level fail
    data
  • Fast physical failure analysis
  • identify failing logic gates/nets or memory cells
    to help rapid yield learning (important for new
    technologies)
  • Automated repair of large memories
  • identify failing memory cells to guide row/column
    replacement

35
Agenda
  • Scan-Based Delay Test
  • Methodology Considerations
  • Delay Test Overview
  • Defect Types
  • Product/Pattern Timing Considerations
  • Advanced Pattern Timing Capabilities
  • Visit http//design.fossil.com
  • Sign up (free)
  • Vote for Irma, Rain Jackal, and berndk
  • Wrap-up Discussion
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