Simulating Front-end Electronics and Integration with End-to-end Simulation

1
Simulating Front-end Electronics and Integration
with End-to-end Simulation

• Fukun Tang
• Enrico Fermi Institute University of
  Chicago

With Karen Byrum and Gary Drake (ANL)
Henry Frisch, Mary Heintz and Harold
Sanders (UC)
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Harolds TOF System

• dum

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Time Stretcher TDC
MCP_PMT Output Signal
Start
500pS
Reference Clock
Stop
Tw
fine time interval
psFront-end
4
IBM SiGe BiCMOS 8HP Process

• 130-nm Technology
• SiGe Hetero-junction Bipolar Transistors
• fT (high performance) 200GHz, BVceo1.7V,
  BVcbo5.9V
• fT (high breakdown) 57GHz, BVceo3.55V,
  BVcbo12V
• High-Q Inductors and Metal-Isolator-Metal
  Capacitors
• 4 Types of Low-tolerance Resistors with Low and
  High Sheet Resistivity
• n Diffusion, Tantalum Nitride, p Polisilicon
  and p- Polisilicon
• Electrically Writable e-Fuse
• CMOS Transistors (VDD1.2V or 2.5/3.3V)
• Twin-well CMOS
• Hyperabrupt Junction and MOS Varactors
• Deep Trench and Shallow Trench Isolations
• 3 to 5 Copper Layers and 2 Aluminum Layers (up to
  3 thick layers)
• Wire-bond or Controlled Collapse Chip Connect
  (C4) Solder-bump Terminals

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Cadence Custom IC Design Flow for IBM 8HP
Design Specification
Library, tech files
Virtuoso Schematic
Schematic Capture
Models
Analog Design Environment (ADE) AMS Design
Environment (AMS)
Circuit Simulations
Tech File, DRC, PCell
Virtuoso XL Layout Chip Assembly Router
Cell/Chip Layout
Verification and RF Parasitic Extraction
IBM 8HP PDK
Tech File , DRC
Assura DRC/LVC, RCX
Post-Layout Simulations
Models, RCX
ADE, AMS Simulations
Tech File
Mask Generation
GDSII Stream Out
Tech, Foundry Rules
Validation
DRC, Filler Generation
Tape-Out
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Interface to Other Simulation Tools
ASCII files Waveform time-value pair
ASCII files Waveform
time-value pair
Tube Output Signals from Simulation
Cadence Virtuoso Analog Environment Or Cadence
Virtuoso AMS Environment
System Simulation Results
Tube Output Signals from Scope
Spectre Netlist
Spectre Library
Spectre Netlist (Cadence Spice)
Custom Chip Schematic
IBM 8HP PDK
Cadence Simulator
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Waveform Time-value Pair Format
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02/2007 MOSIS Submission (2GHz VCO)
2GHz VCO Schematics
Simplified VCO Core Schematic

• SiGe HJT, negative resistance differential VCO
• On-chip high-Q LC tank
• High Frequency PN diode Varactors
• Capacitor voltage dividers
• 50-ohm line drivers

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VCO Simulation Result
Output Waveforms
Phase Noise -97dBc/Hz Equivalents to
Cycle-to-cycle time-jitter of 5 fs
V-F Transfer Function Tuning Range7.5
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Conclusion
We entered a completely different world than most
of us live in. We have lots to learn, lots
need to be done.

• A journey of 1000 miles begins with a single
  step.
• ---Lao Tzu (Laozi), 600 B.C.