DVI Compositors

1
DVI Compositors

• Anselmo Lastra

2
Topics

• DVI Basics
• Metabuffer
• Lightning
• Others
• Sepia
• HP
• ORAD

3
DVI

• Information from DVI 1.0 Specs
• www.ddwg.org
• One or two link options

4
Bandwidth

• Each link can support up to 165 MHz
• The second link meant to support higher res
  devices, like IBM panel
• Second link can also support higher than 24 bits
  of color

5
More Detail

• TMDS Transition Minimized Differential Signaling

6
TMDS

• Pixel for each color channel encoded as 10-bit
  signal
• Encoded from 8 bits to achieve DC balance
• Two stages
• First makes 9-bit transition minimized code from
  8-bit data
• Second stage tries to balance 1s and 0s

7
Transition Minimization
8
Balancing

• Keeps track of how many 0s and 1s sent
• Optionally inverts the 9 bits to try to balance
• 10th bit indicates inverted status

9
Analog/Digital Support

• Normally see analog/digital connectors
• Digital-only doesnt have cross

10
Ideal Interface?

• DVI tried to be compatible
• What would we do if starting from scratch?
• Blanking interval
• Compression
• Temporal coherence
• Smart displays
• Networked

11
Future Standards

• Digital Packet Video Link
• Takes advantage of frame buffer built into the
  display

12
DVI-Based Clusters

• Several possible goals
• Multiple displays, perhaps more than can be
  supported by one PC
• Higher performance to one display
• Higher performance to multiple displays
• Look at several systems

13
Metabuffer

• From UT Austin
• Not clear it was ever built
• Metabuffer refers to a large virtual frame buffer
  representing the aggregate displays
• Renderers write to
• Axis aligned rectangular viewports
• At variable resolutions
• Example foveated displays

14
Approach

• They say sort-middle not appropriate
• True?
• Refer to sort-first system from Princeton
• They target sort-last
• Any processor can access any part of display
  space
• Specify a viewport
• Resolution does not have to match viewport

15
Approach (2)

• A renderers
• Send data over DVI
• Alternate color Z, 30Hz
• B frame buffer to store color Z
• Control info sent on first scanline of a frame
• C composers
• D frame buffers
• E displays w/ DVI

• More detail next

16
Composers

• Data flow from B
• Composers (C) pick off data destined for their
  display
• Composers send data down so pixels can be Z
  composited
• Smart frame buffers (D) can do post processing
• Antialiasing, for example

17
Suggested Implementation

• At least one scan line of buffering in each
  compositor
• For pixel replication

18
Issues

• What about all this buffering?
• Latency might be 2 frames

19
Lightning-2

• Collaboration of Intel, Cornell, and Stanford
  people
• Built at Intel
• Stated requirements
• Scalability to hundreds of PCs
• Independent of host system
• Can use different types and generations of GPUs
• Performance
• They wanted high resolution, high update and
  refresh rates, and low frame latencies

20
Architecture

• Crossbar
• Can be part of sort-first (or sort-middle) system
  to route tiles
• Can be sort-last
• Rows are DVI
• Cols are custom

21
Slices

• 4 slices/board
• JTAG port for programming
• DVI input repeated

• Front and back buffer to pipeline frames
• Compositor can work off one buffer while second
  being filled
• Latency?

22
Compositing Chain

• 533 Mpixels/sec
• Eight 1024x768 projectors
• Runs in scan order
• Pixel data for different displays time
  multiplexed
• Chain 8 pixels wide at 66 MHz
• Pixel is 32 bits. 24-bit color, 8 bit code
• No buffering in chain or at bottom

23
Composition

• Composition in this example is simple just
  overwrites

24
Memory System

• Distribution from input space to output space
• Forward mapping
• Writes irregular
• Need output-space size storage
• Reverse mapping
• Reads irregular
• Needs input-space size storage only
• Needs a data structure to hold input/output
  mapping
• They chose forward mapping

25
Memory System (2)

• They use 2 banks of memory to enable full-speed
  writing and reading
• Need 533 Mpixels/sec bandwidth
• 2.1 GB/s

26
Pixel Mapping

• Need way to specify input -gt output mapping
• They use 2-pixel-wide header (48 bits)
• Always first 2 pixels of scan line
• May be more if multiple tiles per input frame
• See next slide

27
Pixel Mapping Figure
28
Synchronization

• Composition must wait for all renderers to finish
  and transfer frame
• Commodity GPUs dont have frame sync
• They set GPUs to swap on horizontal instead of
  vertical
• The A/B bit identifies scan lines
• State transitions next slide

29
States

• Extra communication makes full output refresh
  rate impossible to sustain
• They increase input refresh rate to accommodate
  the communication

30
Composition

• They implement
• Screen-tile assembly
• Priority
• Color keying
• Depth compositing
• The priority is set using the 8-bit opcode field

31
Depth Compositing

• They had to read back depth to PC and write to
  parts of frame buffer
• Older GPUs, GeForce 2
• Depth sent to display 0 and color to display 1
• Since composition uses time multiplexing for
  display, color available right after depth

32
Depth

• Figure 6 Depth compositing with four rendering
  nodes. Each node renders one quarter of the model
  into the upper-left region of its framebuffer.
  This leaves room around the edges for the depth
  information, which is read out of the depth
  buffer and written back into the color buffer in
  pieces to the right and bottom of the color
  information. Image (a) shows the contribution of
  one rendering node. Image (b) shows the final
  color image as reconstructed by Lightning-2,
  color-coded by rendering node. Image (c) shows
  the final seamless rendering.

33
Board

• Figure 7 Lightning-2 module. The 4 inputs are
  the pairs of white connectors down the left-hand
  edge of the board. The upper connector of each
  pair is the DVI input and the lower connector is
  the repeated output. Visible above each pair is
  the serial port for the back-channel. Each input
  slice stretches out horizontally from its
  associated connectors and consists of an input
  FPGA and 4 FPGAs that map the inputs framebuffer
  and implement the compositing logic. The 8 DVI
  outputs are distributed across the bottom of the
  board. The 3 wide white connectors staggered at
  the top of the board and in a column at the
  bottom of the board carry the compositing chain.

34
Depth Compositing Results
35
Buddha
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Their Conclusions

• Crossbar flexible and predictable
• Cost is memory and other hardware
• As system grows lower percentage of memory used
• The depth compositing has high overhead
• Would be better now, but still 2 frames
• Due to inflexible structure of DVI
• Antialiasing not supported for sort-last
• Could be done, but bandwidth scales
  proportionately

37
Sepia and HP

• PCI
• Readback from GPU
• Connected by proprietary Gigabit network
• Sepia 2 is presumably using DVI
• Theres also compositor from HP workstation group
  out of Colorado Springs

38
Orad

• TV compositor company
• Has a DVI compositor product
• http//www.orad.co.il/

39
Another Option

• Can increase performance by frame interleaving
• SGI Skywriter
• Some of the compositors (HP, maybe others) can do
  this
• The SGI digital switch on Evans

40
Other References

• Metabuffer Web Page
• http//www.ticam.utexas.edu/CCV/projects/DiDi/Meta
  buffer.htm
• Lighting-2 Web Page
• http//graphics.stanford.edu/papers/lightning2/
• DVI standard
• http//www.ddwg.org/