IO in Microprocessors

1
I/O in Microprocessors

• A few definitions
• I/O mechanisms in general
• Representative I/O devices and standards
• Example - The PC I/O system

2
A few definitions

• Bus
• Parallel connection of data, address, and control
  lines
• Usually implemented with parallel traces on
  motherboard and PC edge connectors
• Control lines are typically
• Reset
• INTRx, INTAx, DMARx, DMAGx
• IORD, IOWR, MEMRD, MEMWR
• Address lines split on chip into
• Interface select
• Register select
• Memory/mapped vs port-based I/O
• Memory-mapped
• interface registers look like any other memory
  location
• addressed by normal memory-reference instructions
• Common in processors with unsegmented memory
  space
• Port space
• Interface registers look like I/O ports
• Addressed by special IN/OUT instructions
• Normally used so port space can be seen
  regardless of segmentation

3
More definitions

• Handshaking
• Meaning
• Sequence of signals that allow two entities to
  reach agreement on a transaction
• Can be implemented as logic signals or within
  network packets
• Two-wire is sufficient to handle asynchronous
  data transfer
• One-wire can do some master-slave transactions
• Interface
• Logic that connects external device/s to bus
• Appears as a set of readable and/or writable
  registers to programmer
• Registers are of these types
• Data in reading this causes or observes an I/O
  action
• Data out writing this causes an I/O action
• Control causes a change in interface state
• Status observes interface or device status
• External connection matches some external
  standard examples
• RS-232 serial port
• Centronics parallel port
• Keyboard or PS/2 mouse
• Network (Ethernet)

4
I/O mechanisms in general

• Programmed I/O (PIO)
• Memory-mapped
• Separate I/O port space
• Interrupt
• Uses processor interrupt mechanism and usually
  interrupt controller
• Actual I/O is done by PIO in an interrupt service
  routine (ISR)
• ISR is called only when interrupt occurs
• Polling is a common alternative
• Direct memory access (DMA)
• Separate DMA controller takes temporary control
  of bus when a DMA request comes from the device.
• DMA controller performs I/O operation without CPU
  activity
• Distinctly faster because no instruction fetch or
  environment saving (as in Interrupt activity) is
  needed

5
Characteristics of each mode

• PIO
• Faster than most devices
• Ties up CPU while executing
• Complete control of I/O device
• Interrupt
• Because of interrupt overhead it is slower than
  many devices
• Preferable for handling many slow but
  unpredictable devices
• Setup is more complex
• DMA
• Faster and PIO or interrupt
• Less CPU overhead than PIO or interrupt
• Complex setup and hardware connection
• Only partial control of device errors or
  unusual activity must be handled in CPU

6
Polling

• Polling is periodic checking of each of many
  devices
• Comparison with PIO
• Can handle many devices requesting service
  unpredictably
• More status-checking (are you ready) overhead
• Comparison with Interrupt
• Less hardware complexity (no interrupt
  controller)
• Less flexibility (polling overhead is always
  there even if device is inactive)
• Less initial system setup
• Comparison with DMA
• Much slower
• Less hardware complexity (no DMA controller)
• Cannot do long interleaved transaction
  independently of CPU
• Can handle exceptions more readily

7
Performance criteria

• Speed
• Speed of data transfer product of transfer rate
  and data bus width
• Greatest for DMA, then PIO, interrupt is usually
  slowest
• Latency
• Average or maximum waiting time between service
  request and start of service
• Greatest for PIO, then interrupt, then DMA
• Requirement depends on amount of internal
  buffering in device
• Transaction overhead
• Amount of time per transaction required to effect
  a transfer
• Major disadvantage of interrupt

8
Typical interface internal modem
PCI Edge Connector
RJ-45 Phone connector
9
Contents of a typical interface
Register select
Data lines
High-order address
Select logic Decides if this Interface addressed
Main logic chip Performs most Interface functions
To outside
Chip select line
10
Exceptions, interrupts, and errrors

• Exception
• General term for an event that can cause a break
  in processor or program operation P H uses
  the term in ways 80x86 people use interrupt
• Can be software or hardware
• Trycatch construct in C and Java
• Syscall in MIPS is a software interrupt
• INT in 8086 is a software interrupt
• Interrupt
• In MIPS it means hardware interrupt
• In 80x86 it means either hw or sw
• Both exceptions and interrupts are normal
  happenings
• Error is definitely an unusual condition
• Examples
• Division by 0
• Illegal instruction
• Floating overflow (underflow is often normal in
  iterative computation)

11
Handling of interrupts and errors

• All three are handled the same way
• Save program counter and possibly status
• Jump to a location specified by the operating
  system
• Most machines have an interrupt instruction
• For testing
• For operating system calls

12
I/O and interrupt in the 80x86 family

• Interrupt controller is one-way passes
  interrupt to CPU
• Interrupt controller tells CPU which line
  interrupted
• NMI bypasses interrupt controller and cant be
  disabled inside CPU external circuit is needed
• All other interrupt processing is done by code
  pointed to in the interrupt vector table in low
  memory
• INT, NMI, processor exceptions, and the INT
  instruction all are processed the same way in the
  CPU

INT
CPU of 80x86 tribe
Interrupt controller
Interface
IRQi
NMI
13
I/O and interrupt in 80x86 software

• PIO
• Done by IN AL,port or OUT AL,port
• Port is either DX or a literal 8-bit port number
• Ports greater than 0FFH must be reached by
  setting port number in DX
• This reaches the port space from anywhere in the
  code
• The interrupt mechanism
• Interrupt vectors are long pointers (new IPnew
  CS) in low memory
• The long pointer structure means they can be
  reached from any code segment
• Any interrupt vector can be used by either
• INT n instruction
• Interrupt cycle interrupt controller says which
  vector to use, based on which interrupt line
  caused the interrupt
• Specific interrupt vectors are used by
• Processor exceptions
• NMI uses vector 2

14
When an interrupt arrives

• For all interrupts
• IP, CS, and the flags are pushed
• Flags are set to default (carry off, interrupts
  disabled, etc.)
• Interrupt number is used to select interrupt
  vector
• CS and IP are loaded from the selected IV
• Differences between types
• Software INT n specifies vector n
• INT line cpu does interrupt cycle with
  interrupt controller and gets one byte, which is
  the interrupt number to be used INT can be
  disabled by CLI instruction
• NMI line vector 2 is selected
• Processor exception depending on the type any
  of vectors 0-0FH will be used
• Return from interrupt
• IRET instruction restores flags, CS and IP

15
Representative I/O devices and standards

• Individual digital I/O lines
• Parallel ports
• Serial ports
• A/D
• Timers
• Disks and other mass storage
• Network interfaces
• Note integrated controllers typically include
  most ports and memory on the chip itself

16
Some useful concepts and definitions

• Bus
• Parallel connection usually PC edge connectors
  and traces on motherboard, or ribbon cables
• Signal groups are
• Data bidirectional
• Address unidirectional (but can be driven by
  DMA controller)
• Control transaction control and interrupt/DMA
  request/grant
• Interface
• Device that connects to bus on one side, external
  standard on other
• Has registers of four types
• Data in (reading this usually causes an I/O
  action)
• Data out (writing this causes an I/O action)
• Control (controls interface, not device)
• Status (checks interface , sometimes device
  status)

17
Example - The PC I/O system

• System devices (traditional)
• Keyboard and mouse input processor
• Serial port/s
• Parallel port
• Interrupt controller
• DMA controller
• Floppy controller
• Hard disk controller
• Graphics adapter
• More recent
• USB controller
• PnP devices
• SCSI controllers
• Network cards
• For standards check techfest

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Example typical embedded controller 68HC011

• Check www.motorola.com

19
Typical I/O devices and standards

• Discrete lines
• Parallel I/O
• Serial I/O
• Timers
• Mass storage devices
• ADC and DAC
• Graphic devices
• Network interfaces

20
I/O in the PC
ISA bus, 4.77 MHz (also system bus)

• System devices
• Keyboard and mouse
• Graphics
• Serial and parallel ports
• Interrupt and DMA controllers
• Disk interfaces (floppy and IDE)
• Specialized devices and standards
• Multimedia (sound, DVD)
• USB and firewire (IEEE1394)
• Network interfaces
• PnP standard
• Buses
• ISA
• PCI
• AGP
• System

cpu
memory
interfaces
interrupt controller
Dma controller
Traditional PC
21
More modern PCs
Processor substrate
CPU
I-cache
I-cache
System bus
133 MHz
PCI Bridge
Memory
Graphics
PCI bus
33 MHz
Disk interface
Integrated controller
Network interface
ISA bridge
ISA bus
8 MHz
Legacy cards
22
The PC I/O system port assignments
23
PC devices

• DMA controller
• Some channels hardwired to HD controller, others
  available
• Interrupt controller
• Two controllers 15 real interrupt levels
• Timers these provide the 18.2 HZ NMI interrupt
• Parallel port provides several functions
• Most important is talking to keyboard
  microprocessor
• COM1 and COM2
• One is usually internally simulated by the modem
• Other is the serial connector
• LPT1
• Parallel port connector
• Original (SPP) was output data and input status
  only
• Newer versions (ECP, etc.) can input and do
  handshaking

24
Backward compatibility

• Compatibility effects
• Present PCs dont really have these devices
• The legacy components (serial ports, parallel
  ports, timers) live in the southbridge (a
  combination chip)
• Windows (2K, XP, Vista) no longer allows direct
  access to all the I/O
• DOS-based I/O works partially, but is a useful
  way to learn I/O
• Very quick overview of DOS/BIOS calls
• DOS is/was general, worked on any PC-compatible
  machine
• BIOS is the bootrom supports all devices needed
  for booting
• Interrupt service routines for standard devices
  can also be called directly good luck

25
Using DOS calls

• Command prompt
• In all programsgtaccessories
• Allows direct input of DOS commands this allows
  starting Windows-dumb programs
• A batch file is a primitive script file that runs
  a sequence of DOS commands
• Google for DOS/BIOS calls
• You have seen this in using MASM/LINK/CV
• DOS commands are invoked byMOV AH,function_number
  INT 21HArguments are placed in registers such
  as AL, BX, DX, CXReturn is made using these same
  registers
• A link www.arl.wustl.edu/lockwood/class/cs306/b
  ooks/ar

26
BIOS Calls

• Invoked much like DOS calls exampleMOV AH,
  function_numberINT 10H thru 19H relates to
  device or function groupCalling sequences
  look the same but carry is often used as a
  status indicator
• Keyboard exampleINT 21H, function 6 direct
  console I/O called with AL0ffH, inputs a
  character called with ALanything else, outputs
  that characterINT 16H keyboard
  services Function 0 Read a key from the
  keyboard Function 1 See if a key is
  available Function 2 Return keyboard shift key
  status

27
Direct I/O keyboard example

• Keyboard input (the keypress information) appears
  in register 60H
• The interrupt service routine for the keyboard is
  INT 9H, which normally reads port 60H and stores
  the result in a buffer in lower memory

Serialcable
KeyboardMicroprocessor
MicroprocessoronMotherboard
CPU
IRQ1
InterruptController
INTA, followed by9 for interrupt 9
28
The 80x86 interrupt system

• How it works
• Relationship between INT and CALL instructions
• Implementation

29
I/O and interrupt in the 80x86 family

• Interrupt controller is one-way passes
  interrupt to CPU
• Interrupt controller tells CPU which line
  interrupted
• NMI bypasses interrupt controller and cant be
  disabled inside CPU external circuit is needed
• All other interrupt processing is done by code
  pointed to in the interrupt vector table in low
  memory
• INT, NMI, processor exceptions, and the INT
  instruction all are processed the same way in the
  CPU
• INT is usually used to call system functions from
  anywhere in memory

30
IN and OUT instructions
INTR
INTA
n
Device requests service
Interrupt controller interrupts CPU
CPU asks for interrupt byte (with INTA)
Interrupt controller supplies interrupt byte
CPU jumps as directed by interrupt byte
CPU communicates with Interface using PIO
31
How it works

• Hardware interrupts
• NMI operation
• Edge interrupts the CPU, unmaskably
• Uses interrupt vector 2
• Not routed through the interrupt controller
• INTR/INTA operation
• INTR is issued by the interrupt controllerWhen
  acknowledged the IC sends a one-byte whodunit
  value to the CPU
• CPU then does INT n using this value for n
• Level triggered only acknowledging interrupt
  turns it off
• CLI operation turns off hardware INTRs, but not
  NMI
• This effectively requires an interrupt controller
  to provide the interrupt number

32
CPU interrupt operations

• Interrupt operation
• CPU pushes flags, CS, and IP
• CPU sets flags to predetermined value 2700H
• CPU gets interrupt vector (doubleword) from
  memory location 4n
• CPU goes to the interrupt vector location
• Interrupt return
• CPU pops flags, CS, IP
• This results in a return as though nothing
  happened.
• Area above the stack is disturbed, top-of-stack
  and below are undisturbed

33
Relationship between INT and CALL instructions

• Call near pushes only IP
• RET near is its inverse
• RET n pops extra locations from stack used to
  remove passed parameters
• Call far pushes CS and IP
• RET near is its inverse, restores CS
• INT pushes flags, CS, and IP
• IRET is its inverse.
• Using INT n causes same result regardless of
  current CS value
• Used for system calls (INT 21H)
• Also used to simulate hardware interrupts for
  testing or low-level I/O

34
Implementation in the PC

• PC at this level is running DOS (simulated)
  rather than Windows
• Interrupts 0-7 are CPU exceptions
• Interrupts 8-15 (08H-0FH) are hardware
• Interrupts 10H-1FH are BIOS interrupts
• Interrupts 20H-7FH are DOS interrupts (not all
  used)
• Interrupts 80H-0FFH are user interrupts
• BIOS and DOS interrupts have individual
  functions, specified by AH

35
Interrupt Service Routines

• A routine designed to deal with an interrupt
  coming from a device
• It should be invisible to the program interrupted
• It services the device using programmed I/O
• It must be installed before it can be used
• If you captured an interrupt you should remove it
  before terminating your application
• Some examples
• An ISR for a new interface
• Capturing an existing ISR example hotkey

36
General structure

• Interrupt operation itself saves PC and flags
• Saving environment
• Push whatever registers you plan to use
• I/O action itself
• Sense device status
• Perform appropriate I/O action
• Restoring environment
• Pop whatever registers you pushed
• IRET
• If you are capturing an interrupt (i. e. hotkey)
• Make sure of stack contents before jumping to the
  original ISR

37
The keyboard example
Keyboard Scanning keys For changes
8259 Interrupt controller
CPU
Microprocessor On motherboard
Internal parallel port

• Event sequence
• Keypress or release
• Serial byte sent to motherboard processor(8042)
• 8042 asserts IRQ1
• 8259 causes CPU to do INT9 (1 plus internally
  stored 8)
• CPU reads that byte from internal parallel port,
  and buffers it

38
A few keyboard events
39
The main DOS keyboard functions (INT 21H,
Function n)
40
A few more DOS I/O functions
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Part of the INT 16H functions
42
More INT 16H functions