Overview

1
Overview

• Logic
• Combinational Logic
• Sequential Logic
• Storage Devices
• SR Flip-Flops
• D Flip Flops
• JK Flip Flops
• Registers
• Addressing
• Computer Memory

2
Logical Completeness

• Can implement ANY truth table with AND, OR, NOT.

A B C D
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
1. AND combinations that yield a "1" in the
truth table.
2. OR the resultsof the AND gates.
3
Combinational vs. Sequential

• Combinational Circuit
• always gives the same output for a given set of
  inputs
• ex adder always generates sum and
  carry,regardless of previous inputs
• Sequential Circuit
• stores information
• output depends on stored information (state) plus
  input
• so a given input might produce different
  outputs,depending on the stored information
• example ticket counter
• advances when you push the button
• output depends on previous state
• useful for building memory elements and state
  machines

4
R-S Simple Storage Element

• R is used to reset or clear the element set
  it to zero.
• S is used to set the element set it to one.
• If both R and S are one, out could be either zero
  or one.
• quiescent state -- holds its previous value
• note if a is 1, b is 0, and vice versa
• Out is usually called Q , and the other output
  call Q

1
1
0
1
1
0
1
0
1
1
0
0
1
1
5
Clearing the R-S

• Suppose we start with output 1, then change R
  to zero.

1
0
1
1
0
1
0
Output changes to zero.
1
1
1
0
1
1
0
0
0
Then set R1 to store value in quiescent state.
6
Setting the R-S

• Suppose we start with output 0, then change S
  to zero.

1
1
0
1
0
Output changes to one.
1
0
0
1
0
1
1
Then set S1 to store value in quiescent state.
7
Basic SR Flip Flop
Nor Gates
Nand Gates
8
Clocked SR Flip Flop
9
D Flip Flop (D Latch)
10
D-Latch

• Two inputs D (data) and WE (write enable)
• when WE 1, latch is set to value of D
• S NOT(D), R D
• when WE 0, latch holds previous value
• S R 1

11
Trigger Flip Flop
12
Master Slave Flip Flop
13
Master-Slave D-Latch Flip flop

• A pair of gated D-latches, to isolate next state
  from current state.

During 1st phase (clock1),previously-computed
statebecomes current state and issent to the
logic circuit.
During 2nd phase (clock0),next state, computed
bylogic circuit, is stored inLatch A.
14
Positive Edge Triggered Flip Flop
15
JK Flip Flop
16
JK as a Universal Flip Flop
JK as an SR use set and pre inputs JK as a
Toggle connect J and K JK as a D connect NOT
J to K
17

• Logic Spec Sheets
• Texas Instruments
• http//www.ti.com/hdr_p_logic
• UW
• http//www.ee.washington.edu/stores/

18
Register

• A register stores a multi-bit value.
• We use a collection of D-latches, all controlled
  by a common WE.
• When WE1, n-bit value D is written to register.

19
Recall Representing Multi-bit Values

• Number bits from right (0) to left (n-1)
• just a convention -- could be left to right, but
  must be consistent
• Use brackets to denote range Dlr denotes
  bit l to bit r, from left to right
• May also see Alt149gt, especially in hardware
  block diagrams.

0
15
A 0101001101010101
A20 101
A149 101001
20
Memory

• Now that we know how to store bits,we can build
  a memory a logical k m array of stored bits.

Address Space number of locations(usually a
power of 2)
k 2n locations
Addressability (Word Length) number of bits per
location(e.g., byte-addressable)
m bits
21
1K X 4 SRAM (Part Number 2114N)
22
1K X 4 SRAM (Part Number 2114N)
23
1K X 4 SRAM (Part Number 2114N)
24
Memory Design 1K x 4

A0009 ?
? ? D0300

Addr Block Select ?
25
Memory Design 1K x 8
D0704
D0300
A0009 ?
A0009 ?
? ? D0704
? ? D0300
Addr Block Select gt
Addr Block Select gt
26
Memory Design - 2k x 8
D0704
D0300
Block 00 Block 01
27
Memory Design - 4k x 8
D0704 D0300
Block 00 Block 01 Block 10 Block
11
28
22 x 3 Memory
word select
word WE
input bits
address
write enable
address decoder
output bits
29
More Memory Details

• Two basic kinds of RAM (Random Access Memory)
• Static RAM (SRAM)
• fast, maintains data as long as power applied
• Dynamic RAM (DRAM)
• slower but denser, bit storage decays must be
  periodically refreshed

Also, non-volatile memories ROM, PROM, flash,