EECE 631 Microcomputer System Design Lecture 15

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EECE 631Microcomputer System DesignLecture 15

• Spring 2008
• Chris Lewis
• clewis_at_ksu.edu

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DAC Dynamic Performance Specs

• Settling Time
• Glitch Impulse Area
• Harmonic Distortion
• Signal-to-Noise Ratio
• Audio Specific Specifications

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What do they tell us?

• Settling Time
• How long we need to wait after an input change
  until the output is within 1/2 LSB. Gives a
  good idea of the maximum rate of change that the
  DAC can be used for.

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Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
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Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
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What do they tell us?

• Settling Time
• Glitch Impulse Area

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(No Transcript)
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Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
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Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
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What do they tell us?

• Settling Time
• Glitch Impulse Area
• Harmonic Distortion
• How much distortion you will get if you expect to
  put out a specified waveform.

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What do they tell us?

• Settling Time
• Glitch Impulse Area
• Harmonic Distortion
• Signal-to-Noise Ratio

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What do they tell us?

• Settling Time
• Glitch Impulse Area
• Harmonic Distortion
• Signal-to-Noise Ratio
• Audio Specific Specifications

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Sampling Rate

• Nyquists Criteria
• An Analog signal with a bandwidth of fa MUST be
  sampled at a rate fs gt 2fa to avoid loss of
  information.
• If fs lt 2fa then a phenomena called aliasing will
  occur in the analog signal bandwidth

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Time Domain Effects of Aliasing
Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
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Analog to Digital Converter

• Types
• Flash
• Counter
• Hybrid
• Integrating
• Sigma-Delta
• Others exist
• Static Performance Specifications
• Dynamic Performance Specifications

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Flash ADC
Source www.stanford.edu/class/ee315/handouts/HO20
_ADC.pdf
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Counter ADC
Source www.upscale.utoronto.ca/GeneralInterest/
Drummond/Micro/ln_a_d.pdf
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Successive Approximation ADC
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Hybrid ADC

• Several types
• Convert the M most significant bits with a
  successive approximation ADC and the N least
  significant bits with a Flash ADC for a MN bit
  converter
• Convert the M most significant bits with a flash
  ADC

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Integrating ADC Single Slope
Source www.stanford.edu/class/ee315/handouts/HO20
_ADC.pdf
21
Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
22
Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
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Source Analog Devices, Mastering the Mix in
Signal Processing, Mixed-Signal Design Seminar,
1991
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ADC Comparison
Source www.upscale.utoronto.ca/GeneralInterest/
Drummond/Micro/ln_a_d.pdf
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Last Lab
Headphone Jack
Signal Conditioning
ADC
FIR/IIR Filter
SPI
DAC
Signal Amplification
Headphones
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Signal Conditioning

• Why?
• -1 to 1 Volts
• Higher input impedance
• How?
• Op-Amp
• DC offset

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System Interrupts

• NEED CHECK All these to determine cause of
  interrupt
• PIT_SR PITS
• RTT_SR RTTINC ALMS
• WDT_SR WDERR WDUNF
• DBGU_SR All bits and DBGU_MR
• PMC_SR All bits and PMC_IMR
• RSTC_SR BODSTS URSTS

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Modes of the CPU CPSR

• Usersupervisor modes
• System Mode
• IRQ mode
• FIRQ mode
• Abort mode
• Undefined

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Various Registers
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Read the handout, thoroughly
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Common questions and Issues

• Debugger continuously reads AIC_IVR
• Reading clears interrupt unless protected
• AIC_DEBUG PROT1 requires manual clearing
• 0x18 LDR PC, PC, -0xF20 would clear
  interrupt at AIC if PROT ! 1
• AIC_ICCR should be used if PROT 1

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Tracking the elusive interruption that does not
occur Start at the source

• Run program long enough that you expect the
  interrupt should have occurred
• Breakpoint at 0x18
• Breakpoint in ISR
• View the status register of the peripheral that
  should be generating the interrupt
• If interrupt bit is not set, enable interrupt in
  the peripheral
• If interrupt bit is set, make sure it is not
  masked

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PERIPHERAL IRQ goes to AIC

• Once you are certain that the interrupt is
  occurring and unmasked at the peripheral, view
  the AIC registers
• You may want to edit the .ddf file to allow
  direct viewing of all associated registers, since
  it has not been done right for our chip

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IDE Custom Config

• ioat91sam7s256.ddf
• Sfr
• Register definition for SYS
  peripheral
• Register definition for AIC
  peripheral
• sfr "AIC_SMR0", "Memory", 0xfffff000, 4,
  base16
• sfr "AIC_SMR0.PRIOR", "Memory", 0xfffff000, 4,
  base16, bitRange0-2
• sfr "AIC_SMR0.SRCTYPE", "Memory", 0xfffff000,
  4, base16, bitRange5-6
• sfr "AIC_SMR1", "Memory", 0xfffff004, 4,
  base16
• sfr "AIC_SMR1.PRIOR", "Memory", 0xfffff004, 4,
  base16, bitRange0-2
• sfr "AIC_SMR1.SRCTYPE", "Memory", 0xfffff004,
  4, base16, bitRange5-6
• sfr "AIC_SVR0", "Memory", 0xfffff080, 4,
  base16
• sfr "AIC_SVR1", "Memory", 0xfffff084, 4,
  base16
• sfr "AIC_IVR", "Memory", 0xfffff100, 4,
  base16
• sfr "AIC_FVR", "Memory", 0xfffff104, 4,
  base16
• sfr "AIC_ISR", "Memory", 0xfffff108, 4,
  base16
• sfr "AIC_IPR", "Memory", 0xfffff10c, 4,
  base16
• sfr "AIC_IMR", "Memory", 0xfffff110, 4,
  base16

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Common AIC problems

• Interrupt has to be enabled twice here
• AIC_MR
• AIC_DEBUG.GMSK
• AIC_IPR tells which interrupts are pending
• Interrupts that are masked may be pending
• Interrupts with lower priority may be pending
• AIC_IMR tells which are masked
• AIC_CISR indicates signal to core,
• until set, no interrupt at core
• Never viewed as set while AIC_DEBUGPROT 0 WHY?
• If CISR has interrupt set, and cpu does not move
  PC to 0x18, then CPSR bits not enabling
  interrupts
• __enable_interrupt()
• __set_CPSR(0x5F)

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Review

• Enable Interrupt lots of places
• Peripheral
• Mask
• Enable
• AIC
• Mask
• GMSK
• CORE
• CPSR.nirq

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Interrupt occurs at least oncePC0x18

• ISR does not get executed
• Branch Op code not written to 0x18
• SIVRmy_irq ! address of my function
• ISR gets executed only once, maybe twice
• Interrupt not reset
• Clear at AIC, read AIC_IVR will do if PROT not
  set
• AIC_ICCR
• AIC_EOICR, written at end of interrupt function
• use __irq __arm void my_isr()
• ISR gets re-executed, but main loop does not
  progress
• Interrupt not cleared

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AT91F_AIC_Open()

• Disables and Clears all interrupts
• AIC_IDCR
• AIC_ICCR
• Sets all vector table default function
• AIC_SVRi default_handler
• This ensures that if an unexpected interrupt
  occurs, it runs actual code
• Sets default priority and type AIC_SMR
• Writes to IRQ and FIRQ 0x18 and 0x1C respectivley
• Usually this should be the branch opcode LDR PC,
  PC, -F20
• AT91C_AIC_BRANCH_OPCODE
• Sets spurious handler
• Sets AIC_DCR to mode selected
• PROT
• GMSK
• Passing function names as parameters
• A function name is an address 32 bits
• An Opcode is also 32 bits Either works
• Type casting of a function name is same process
  as for variables

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Schedule

• No more formal labs. Project, work on your own
  schedule.
• April 4 Complete and turn in a "paper design"
  include
• Users Manual
• Schematics
• High Level Algorithm
• Parts requirements
• Processor selection
• Description of extent of expected completion of
  each aspect of project
• 13. Monday April 9 EXAM 2.
• 14. Apr.17, 18 ORAL STATUS REPORT GIVEN IN LAB
• 10 minutes
• Half by each student
• 15. Apr 18 Homework Timing Problem
• 16 Apr 30 Monday - Project must be demonstrated
  by 430 P.M.
• Demonstration is graded
• Prepare to present your work in its best light
• 17 May 2 Wed. Final Report due by 430 P.M.
• 18. May 3 Thursday. - Parts must be turned-in by
  330 P.M, otherwise, your team fails the course.
• 19. May 4 Friday. - Last day of classes for the
  semester.

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My Role in your project

• Debugging
• Technical advice
• Find resources
• You are ultimately responsible for the final
  outcome of your project
• You are responsible for getting along with and
  determining responsibilities of your partner
• You are responsible for source code control
• Partners receive same grade unless
• Obvious to me that one blatantly under performed
• Report indicates a substantial difference in
  effort
• Assigning grades

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Things we missed

• TPU-Time processing unit
• Measure pulse width
• Watch for sequence of pulses
• Interpret sequence of pulses
• SPI-Synchronous Peripheral Interface (serial)
• Flash Memory
• Displays
• ADC and DACs
• Radios

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Remaining Topics

• Timing
• Adding external memory or peripherals
• General Discussion of RTOS topics
• Report writing
• Overview of History and State of
  micro-controllers, role of FPGAs etc.
• Suggestions?