Title: EECE 631 Microcomputer System Design Lecture 19: Timing
1EECE 631Microcomputer System DesignLecture 19
Timing
- Spring 2008
- Chris Lewis
- clewis_at_ksu.edu
2Timing Diagrams for the Memory
Twc on both Read and Write
3Memory Requires Twc to be at least 5570ns
NOT HERE
4Address and Chip Select are same according to text
2.5ns accounts for rise and fall times relative
to cpmck My best guess is that rise and fall
times are 1.25 and 2.5ns MCK is 40 MHz, or 25ns,
therefore, we need Twc minimum allowed by memory
is 5570ns SMC_7 gt Twc (n1)t_cpmck -1.25 gt 5570
(inequality equation) N gt 2 for this to work
5Next Parameter Tcw
6Chip Select to end of write
7Add to CPU timing diagram
8Memory requires the time between chip select
going low till write goes high to be greater than
45(55) or 60(70) ns
- How long does the CPU guarantee that same time to
be? - SMC_18(provided as a min) relates these two
signals, however, it measures from end of chip
select, not the beginning - SMC_7-SMC_18 gt Tcw
- (n1)t_ncpmck-5.tgt45,60
9Next Parameter Tas
10Address to WE
Tas, WE cant occur Prior to address
11Add to CPU timing diagram
SMC_26
Smc_18
12Problem
- (SMC_7 SMC_18 SMC_26)_min gt Tas
- SMC_7_min SMC_18_max-SMC_26_maxgtTas
- This would have been nice max vals not given
- Refer to previous description to determine
- WE occurs ½ clock cycle after address and CS
- 1/2MCK rise time gt Tas (0ns)
13Next Parameter Taw
14Taw mins(45,60 ns)
15Add to CPU timing diagram
16Problem
- min(SMC_7 SMC_18) gt Taw
- Min(SMC_7) Max(SMC_18) gt Taw
- This would have been nice max vals not given
- Refer to previous description to determine
- WE occurs ½ clock cycle after address and CS
- ½ Tclk t_rise Min(SMC_27) gt Taw
- ½ Tcpmck-t_rise(n1)tcmck-2.5gtTaw
17Next Parameter Twp
18Twp mins(40,50 ns)
19Add to CPU timing diagram
SMC_27
SMC_26
20Inequality
21Next Parameter Twr
22Twr mins0
Address must Be valid at end Of WE pulse
23Add to CPU timing diagram
SMC_27
SMC_26