ComputerAided IC Design

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Computer-Aided IC Design

• Laboratory Exercise 1

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Laboratory Exercise 1

• Objective
• To get familiar with Cadence that will be used
  in the labs during entire semester.
• Lab.1a Design a 4-bit register
• Lab.1b Investigate the design of a 3232
  memory and the creation of a full simulation to
  test a memory array, and the memory read
  performance

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Laboratory Exercise 1
Library
Symbol Functional model (simulation) Footprint
(APR) Timing model
Schematics (Cadence)
LVS
Layout (Cadence)
Extraction (Cadence)
Characterization SPICE
DRC
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Laboratory Design Tools

• Commercial CAD tools
• - Cadence, Synopsys, etc.
• Commercial software is powerful, but very complex
• - Designers sent to long training classes
• - Students will benefit from using the software,
  
• but we dont have the long training.

• TAs have experience with the software
• Start work EARLY in the lab
• - Plan designs carefully and save work
  frequently

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Start with Cadence Tutorial

• X-win http//www.starnet.com
• X-Manager
• - setting the configuration carefully.
• Lets look at the procedure.

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Steps for Lab.1a

• Follow the tutorial and make an inverter
• Optimize the inverter minimize the width and
  the height
• Characterize the inverter for input rise time and
  output load capacitance
• Build a one bit memory cell and test it
• Make a single 4-bit register cell

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CMOS Inverter
Vdd!
output
input
gnd!
Schematic(Virtuoso)
Layout
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Operation of the register cell

• 3 data lines data in (dc), data out (da, db)
• 3 control lines write (sc), read (sa, sb)
• Core of the memory cell blue box
• sc 0 write
• sc 1 read (break the feedback loop)

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4-bit register

• Tile 4 one bit register cells sharing the control
  lines.
• - 3 control lines
• - 12 data lines
• Test the 4-bit cell
• - write a 1 in all cells -gt read it!
• -gt write a 0 in the cells -gt read it!

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Introduction to CMOS VLSI Design

• Laboratory Exercise 1B

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Objective

• Given the RC model for a memory cell, build the
  path with the worst access time for a1KB ram.
• Determine the worst access time using Hspice.
  Consider both the rising and falling transitions.
  
• Tools used will include HSpice and Awaves.

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Steps for Lab.1b

• Decoder consisting of 32 rows (outputs) and 10
  columns will be provided.
• Model RC delay for the memory cell.
• Construct schematic for the worst delay path of
  3232(1K) memory array.
• Connect memory array to decoder
• Implement simulation deck to test memory array
• Measure the worst case access time.

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Hspice
Required first line of input file To set
conditions of simulation, initial values
Attaching Library, subcircuit and other data
files Netlist of circuit being simulated Input
sources to the circuit Statements specifying type
and conditions of analysis Specifying output
variables and measure statements Changing
analysis points, libraries etc Required last line
of input file
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Statements

• .IC statement
• .ic V(n1) 1
• .MEASURE statement
• .measure tran del trig v(clk) val 1.5V rise1
  targ V(out) val0V fall1

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Statements ...

• Piece-wise Linear (PWL)
• Va0_in a0_in 0 pwl (0 0 50p 0 60p 1.5V)
• PULSE
• Vin node1 node2 PULSE init_val pulse_val delay
  rise_time fall_time duration period
• Vclk clk 0 PULSE 0V 1.7V 0 70p 70p 230p 70p

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PULSE

• Format
• Vin node1 node2 PULSE init_val pulse_val delay
  rise_time fall_time duration period
• Example
• Vin a0_in b0_in PULSE 0V 1.5V 300p 100p 100p 400p
  1000p

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RC model

• pi and T Distributed RC line
• Compute corresponding R and C value
• Measure the worst-case of the access time for
  bitline outputs

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Interconnect and simulate

• Interconnecting the decoder and memory array
• - using Virtuoso Schematic Composer
• Generate HSPICE netlist and modify the netlist
• Find out inputs causing worst-case access time.
• - Perform transistor-level simulation

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Grading / Submission

• Lab.1a 75 of the whole lab.1 points
• Lab.1b 25 of the whole lab.1 points
• Use cover file to check the material/ printouts
  that you need to attach to your lab1a and lab 1b
  report
• Bonus for early submission 5 per working day
  (maximum 10)
• Penalty for late submission 5 per working day
  (maximum 25)